clk: renesas: r9a08g045: Add PCIe clocks and resets

Add clocks and resets for the PCIe IP available on the Renesas RZ/G3S
SoC.  The clkl1pm clock is required for PCIe link power management (PM)
control and should be enabled based on the state of the CLKREQ# pin.
Therefore, mark it as a no_pm clock to allow the PCIe driver to manage
it during link PM transitions.

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250704161410.3931884-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index 643dec45e39d75d8f4f6c9b6df74a6c6d3479cc5..c4639ad22b8b529d5537675344f37f748ad02e51 100644 (file)
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -292,6 +292,10 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
                                        MSTOP(BUS_MCPU2, BIT(14))),
        DEF_MOD("tsu_pclk",             R9A08G045_TSU_PCLK, R9A08G045_CLK_TSU, 0x5ac, 0,
                                        MSTOP(BUS_MCPU2, BIT(15))),
+       DEF_MOD("pci_aclk",             R9A08G045_PCI_ACLK, R9A08G045_CLK_M0, 0x608, 0,
+                                       MSTOP(BUS_PERI_COM, BIT(10))),
+       DEF_MOD("pci_clkl1pm",          R9A08G045_PCI_CLKL1PM, R9A08G045_CLK_ZT, 0x608, 1,
+                                       MSTOP(BUS_PERI_COM, BIT(10))),
        DEF_MOD("i3c_pclk",             R9A08G045_I3C_PCLK, R9A08G045_CLK_TSU, 0x610, 0,
                                        MSTOP(BUS_MCPU3, BIT(10))),
        DEF_MOD("i3c_tclk",             R9A08G045_I3C_TCLK, R9A08G045_CLK_P5, 0x610, 1,
@@ -336,6 +340,13 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
        DEF_RST(R9A08G045_ADC_PRESETN, 0x8a8, 0),
        DEF_RST(R9A08G045_ADC_ADRST_N, 0x8a8, 1),
        DEF_RST(R9A08G045_TSU_PRESETN, 0x8ac, 0),
+       DEF_RST(R9A08G045_PCI_ARESETN, 0x908, 0),
+       DEF_RST(R9A08G045_PCI_RST_B, 0x908, 1),
+       DEF_RST(R9A08G045_PCI_RST_GP_B, 0x908, 2),
+       DEF_RST(R9A08G045_PCI_RST_PS_B, 0x908, 3),
+       DEF_RST(R9A08G045_PCI_RST_RSM_B, 0x908, 4),
+       DEF_RST(R9A08G045_PCI_RST_CFG_B, 0x908, 5),
+       DEF_RST(R9A08G045_PCI_RST_LOAD_B, 0x908, 6),
        DEF_RST(R9A08G045_I3C_TRESETN, 0x910, 0),
        DEF_RST(R9A08G045_I3C_PRESETN, 0x910, 1),
        DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0),
@@ -349,6 +360,10 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
        MOD_CLK_BASE + R9A08G045_VBAT_BCLK,
 };
 
+static const unsigned int r9a08g045_no_pm_mod_clks[] = {
+       MOD_CLK_BASE + R9A08G045_PCI_CLKL1PM,
+};
+
 const struct rzg2l_cpg_info r9a08g045_cpg_info = {
        /* Core Clocks */
        .core_clks = r9a08g045_core_clks,
@@ -365,6 +380,10 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info = {
        .num_mod_clks = ARRAY_SIZE(r9a08g045_mod_clks),
        .num_hw_mod_clks = R9A08G045_VBAT_BCLK + 1,
 
+       /* No PM modules Clocks */
+       .no_pm_mod_clks = r9a08g045_no_pm_mod_clks,
+       .num_no_pm_mod_clks = ARRAY_SIZE(r9a08g045_no_pm_mod_clks),
+
        /* Resets */
        .resets = r9a08g045_resets,
        .num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */