drm/amd/display: Add debug flags for USB4 DP link training.

[Why & How]
Additional debug flags that can be useful for testing USB4 DP
link training.

Add flags:
- 0x2 : Forces USB4 DP link to non-LTTPR mode
- 0x4 : Extends status read intervals to about 60s.

Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 56aaab22fa425893b9e33dd02e86cefc6ec0ea32..54662d74c65acfdd07ca5e1844b8cc8a1013cd88 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -4527,6 +4527,12 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
                else
                        link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
        }
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+       /* Check DP tunnel LTTPR mode debug option. */
+       if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
+           link->dc->debug.dpia_debug.bits.force_non_lttpr)
+               link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
+#endif
 
        if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
                /* By reading LTTPR capability, RX assumes that we will enable

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
index bb2efce67f0d21b056bdd26a5ca55ebbed10dd11..9c620b61f64e6ba074a4495d13c14fe8065314f7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
@@ -534,6 +534,12 @@ static uint32_t dpia_get_eq_aux_rd_interval(const struct dc_link *link,
                                dp_translate_training_aux_read_interval(
                                        link->dpcd_caps.lttpr_caps.aux_rd_interval[hop - 1]);
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+       /* Check debug option for extending aux read interval. */
+       if (link->dc->debug.dpia_debug.bits.extend_aux_rd_interval)
+               wait_time_microsec = DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US;
+#endif
+
        return wait_time_microsec;
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 5185c2d512f79acff7c2e1c31e164fd7b02427fe..dd995905b0cb6c22d0f58ae788645dd379cc2a89 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -499,7 +499,9 @@ union root_clock_optimization_options {
 union dpia_debug_options {
        struct {
                uint32_t disable_dpia:1;
-               uint32_t reserved:31;
+               uint32_t force_non_lttpr:1;
+               uint32_t extend_aux_rd_interval:1;
+               uint32_t reserved:29;
        } bits;
        uint32_t raw;
 };

diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h
index 28e68be41123309ab7a50f4ec189716125f280ad..974d703e37717b091b097a4fccbc897d8d189236 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h
@@ -35,6 +35,9 @@ struct dc_link_settings;
 /* The approximate time (us) it takes to transmit 9 USB4 DP clock sync packets. */
 #define DPIA_CLK_SYNC_DELAY 16000
 
+/* Extend interval between training status checks for manual testing. */
+#define DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US 60000000
+
 /** @note Can remove once DP tunneling registers in upstream include/drm/drm_dp_helper.h */
 /* DPCD DP Tunneling over USB4 */
 #define DP_TUNNELING_CAPABILITIES_SUPPORT 0xe000d