#define   WDT_TIMEOUT_STATUS_BOOT_SECONDARY    BIT(1)
 #define WDT_CLEAR_TIMEOUT_STATUS       0x14
 #define   WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION    BIT(0)
+#define WDT_RESET_MASK1                0x1c
+#define WDT_RESET_MASK2                0x20
 
 /*
  * WDT_RESET_WIDTH controls the characteristics of the external pulse (if
 
        if ((of_device_is_compatible(np, "aspeed,ast2500-wdt")) ||
                (of_device_is_compatible(np, "aspeed,ast2600-wdt"))) {
+               u32 reset_mask[2];
+               size_t nrstmask = of_device_is_compatible(np, "aspeed,ast2600-wdt") ? 2 : 1;
                u32 reg = readl(wdt->base + WDT_RESET_WIDTH);
 
                reg &= wdt->cfg->ext_pulse_width_mask;
                        reg |= WDT_OPEN_DRAIN_MAGIC;
 
                writel(reg, wdt->base + WDT_RESET_WIDTH);
+
+               ret = of_property_read_u32_array(np, "aspeed,reset-mask", reset_mask, nrstmask);
+               if (!ret) {
+                       writel(reset_mask[0], wdt->base + WDT_RESET_MASK1);
+                       if (nrstmask > 1)
+                               writel(reset_mask[1], wdt->base + WDT_RESET_MASK2);
+               }
        }
 
        if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) {