drm/amd/display: DCE12 num_timing_generators should be 6

We should also use it to determine pipe count.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index b6bdd1d529227aa9e2289b64084d115920dc90c3..b13abb025e1b17ca57580c3c1839f3b7bc880850 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -426,7 +426,7 @@ static const struct bios_registers bios_regs = {
 };
 
 static const struct resource_caps res_cap = {
-               .num_timing_generator = 3,
+               .num_timing_generator = 6,
                .num_audio = 7,
                .num_stream_encoder = 6,
                .num_pll = 6,
@@ -909,7 +909,7 @@ static bool construct(
        pool->base.funcs = &dce120_res_pool_funcs;
 
        /* TODO: Fill more data from GreenlandAsicCapability.cpp */
-       pool->base.pipe_count = 6;
+       pool->base.pipe_count = res_cap.num_timing_generator;
        pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 
        dc->public.caps.max_downscale_ratio = 200;