/* We don't have interrupts for link changes, so we need to poll */
        ds->pcs_poll = true;
 
+       /* Set min a max ageing value supported */
+       ds->ageing_time_min = 7000;
+       ds->ageing_time_max = 458745000;
+
        return 0;
 }
 
        mutex_unlock(&priv->reg_mutex);
 }
 
+static int
+qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
+{
+       struct qca8k_priv *priv = ds->priv;
+       unsigned int secs = msecs / 1000;
+       u32 val;
+
+       /* AGE_TIME reg is set in 7s step */
+       val = secs / 7;
+
+       /* Handle case with 0 as val to NOT disable
+        * learning
+        */
+       if (!val)
+               val = 1;
+
+       return regmap_update_bits(priv->regmap, QCA8K_REG_ATU_CTRL, QCA8K_ATU_AGE_TIME_MASK,
+                                 QCA8K_ATU_AGE_TIME(val));
+}
+
 static int
 qca8k_port_enable(struct dsa_switch *ds, int port,
                  struct phy_device *phy)
        .get_strings            = qca8k_get_strings,
        .get_ethtool_stats      = qca8k_get_ethtool_stats,
        .get_sset_count         = qca8k_get_sset_count,
+       .set_ageing_time        = qca8k_set_ageing_time,
        .get_mac_eee            = qca8k_get_mac_eee,
        .set_mac_eee            = qca8k_set_mac_eee,
        .port_enable            = qca8k_port_enable,
 
 #define   QCA8K_VTU_FUNC1_BUSY                         BIT(31)
 #define   QCA8K_VTU_FUNC1_VID_MASK                     GENMASK(27, 16)
 #define   QCA8K_VTU_FUNC1_FULL                         BIT(4)
+#define QCA8K_REG_ATU_CTRL                             0x618
+#define   QCA8K_ATU_AGE_TIME_MASK                      GENMASK(15, 0)
+#define   QCA8K_ATU_AGE_TIME(x)                                FIELD_PREP(QCA8K_ATU_AGE_TIME_MASK, (x))
 #define QCA8K_REG_GLOBAL_FW_CTRL0                      0x620
 #define   QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN            BIT(10)
 #define QCA8K_REG_GLOBAL_FW_CTRL1                      0x624