drm/amdgpu: loose check for umc poison mode

No need to check poison setting for each channel, check for umc0
channel0 is enough.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
index 47452b61b6155cc9b090ca5214a0637c65b996ff..e613511e07e12fd291bd2e72be876572bb9c58fa 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
@@ -451,21 +451,13 @@ static uint32_t umc_v6_7_query_ras_poison_mode_per_channel(
 
 static bool umc_v6_7_query_ras_poison_mode(struct amdgpu_device *adev)
 {
-       uint32_t umc_inst        = 0;
-       uint32_t ch_inst         = 0;
        uint32_t umc_reg_offset  = 0;
 
-       LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
-               umc_reg_offset = get_umc_v6_7_reg_offset(adev,
-                                                       umc_inst,
-                                                       ch_inst);
-               /* Enabling fatal error in one channel will be considered
-                  as fatal error mode */
-               if (umc_v6_7_query_ras_poison_mode_per_channel(adev, umc_reg_offset))
-                       return false;
-       }
-
-       return true;
+       /* Enabling fatal error in umc instance0 channel0 will be
+        * considered as fatal error mode
+        */
+       umc_reg_offset = get_umc_v6_7_reg_offset(adev, 0, 0);
+       return !umc_v6_7_query_ras_poison_mode_per_channel(adev, umc_reg_offset);
 }
 
 const struct amdgpu_ras_block_hw_ops umc_v6_7_ras_hw_ops = {