Fix unlock_ram_in_cache() problem on PCIPPC2/6 boards

(always invalidate cache after unlocking it)

diff --git a/CHANGELOG b/CHANGELOG
index 404b7700db6400c7777204d7783ddcd899a81bff..451676f5cdb03d11f4e5264d0bf6d9ee8deb7d9c 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 Modifications for 1.2.0:
 ======================================================================
 
+* Fix unlock_ram_in_cache() problem on PCIPPC2/6 boards
+  (always invalidate cache after unlocking it)
+
 * Fix ethernet address handling ion case of multiple interfaces
 
 * Patch by Denis Peter, 29 Jul 2002:

diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c
index e8993fce311053649fe1eb4615b6ae6c4196005f..8e0bc0ec498699791733fb4724c2863061ec3ed0 100644 (file)
--- a/board/cray/L1/L1.c
+++ b/board/cray/L1/L1.c
@@ -272,7 +272,8 @@ u8 thing;
 /* .. return NULL means it wasnt mine, non-null means I got it..*/
 u8 *dhcp_vendorex_proc(u8 *pop)
 {
-u8 oplen,*sub_op, sub_oplen,thing = 0, *retval;
+u8 oplen,*sub_op, sub_oplen, *retval;
+u8 thing = 0;
 
        retval = NULL;
        oplen = *(pop + 1);

diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c
index 41e07fed5cd7475dc3071583c20a8c087909f5f2..d22359b3a19fb6ba620aa8e63aa2871e47097511 100644 (file)
--- a/board/pcippc2/pcippc2.c
+++ b/board/pcippc2/pcippc2.c
@@ -86,7 +86,7 @@ int board_pre_init (void)
 
        out32 (REG (CPC0, SIOC0), 0x30000000);
 
-       out32 (REG (CPC0, ABCNTL), 0xB0000000);
+       out32 (REG (CPC0, ABCNTL), 0xF0000000);
 
        out32 (REG (CPC0, SESR), 0x00000000);
        out32 (REG (CPC0, SEAR), 0x00000000);

diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S
index e891e25fdfe6c0c440a724cb4ab5d487b42efb5d..6ce04793bd345249042eb560b4429588cce14e65 100644 (file)
--- a/cpu/74xx_7xx/start.S
+++ b/cpu/74xx_7xx/start.S
@@ -848,10 +848,12 @@ unlock_ram_in_cache:
        sync                    /* Wait for all icbi to complete on bus */
        isync
 
-       /* Unlock the data cache */
+       /* Unlock the data cache and invalidate it */
        mfspr   r0, HID0
        li      r3,0x1000
        andc    r0,r0,r3
+       li      r3,0x0400
+       or      r0,r0,r3
        sync
        mtspr   HID0, r0
        sync