static struct fsl_usb2_platform_data otg_device_pdata = {
        .operating_mode = FSL_USB2_DR_DEVICE,
        .phy_mode       = FSL_USB2_PHY_UTMI,
+       .workaround     = FLS_USB2_WORKAROUND_ENGCM09152,
 };
 
 static int otg_mode_host;
 
 static struct clk *mxc_ahb_clk;
 static struct clk *mxc_usb_clk;
 
+/* workaround ENGcm09152 for i.MX35 */
+#define USBPHYCTRL_OTGBASE_OFFSET      0x608
+#define USBPHYCTRL_EVDO                        (1 << 23)
+
 int fsl_udc_clk_init(struct platform_device *pdev)
 {
        struct fsl_usb2_platform_data *pdata;
 void fsl_udc_clk_finalize(struct platform_device *pdev)
 {
        struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+#if defined(CONFIG_ARCH_MX35)
+       unsigned int v;
+
+       /* workaround ENGcm09152 for i.MX35 */
+       if (pdata->workaround & FLS_USB2_WORKAROUND_ENGCM09152) {
+               v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR +
+                               USBPHYCTRL_OTGBASE_OFFSET));
+               writel(v | USBPHYCTRL_EVDO, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR +
+                               USBPHYCTRL_OTGBASE_OFFSET));
+       }
+#endif
 
        /* ULPI transceivers don't need usbpll */
        if (pdata->phy_mode == FSL_USB2_PHY_ULPI) {
 
        enum fsl_usb2_operating_modes   operating_mode;
        enum fsl_usb2_phy_modes         phy_mode;
        unsigned int                    port_enables;
+       unsigned int                    workaround;
 
        int             (*init)(struct platform_device *);
        void            (*exit)(struct platform_device *);
 #define FSL_USB2_PORT0_ENABLED 0x00000001
 #define FSL_USB2_PORT1_ENABLED 0x00000002
 
+#define FLS_USB2_WORKAROUND_ENGCM09152 (1 << 0)
+
 struct spi_device;
 
 struct fsl_spi_platform_data {