{
        u32 packet_header;
        u32 int_mask;
-       int ret;
+       unsigned long time_left;
 
        tegra_i2c_flush_fifos(i2c_dev);
 
        dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
                i2c_readl(i2c_dev, I2C_INT_MASK));
 
-       ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
+       time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
+                                               TEGRA_I2C_TIMEOUT);
        tegra_i2c_mask_irq(i2c_dev, int_mask);
 
-       if (ret == 0) {
+       if (time_left == 0) {
                dev_err(i2c_dev->dev, "i2c transfer timed out\n");
 
                tegra_i2c_init(i2c_dev);
                return -ETIMEDOUT;
        }
 
-       dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
-               ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
+       dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
+               time_left, completion_done(&i2c_dev->msg_complete),
+               i2c_dev->msg_err);
 
        if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
                return 0;