upper_32_bits(to_hr_hw_page_addr(mtts[0])));
        hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H);
 
-       context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1]));
-       qpc_mask->rq_nxt_blk_addr = 0;
-
-       hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H,
-                    upper_32_bits(to_hr_hw_page_addr(mtts[1])));
-       hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H);
+       if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
+               context->rq_nxt_blk_addr =
+                               cpu_to_le32(to_hr_hw_page_addr(mtts[1]));
+               qpc_mask->rq_nxt_blk_addr = 0;
+               hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H,
+                            upper_32_bits(to_hr_hw_page_addr(mtts[1])));
+               hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H);
+       }
 
        return 0;
 }