#define   TX_TRAINING_EN                       REG_BIT(31)
 #define   TAP2_DISABLE                         REG_BIT(30)
 #define   TAP3_DISABLE                         REG_BIT(29)
+#define   CURSOR_PROGRAM                       REG_BIT(26)
+#define   COEFF_POLARITY                       REG_BIT(25)
 #define   SCALING_MODE_SEL_MASK                        REG_GENMASK(20, 18)
 #define   SCALING_MODE_SEL(x)                  REG_FIELD_PREP(SCALING_MODE_SEL_MASK, (x))
 #define   RTERM_SELECT_MASK                    REG_GENMASK(5, 3)
 
        /* Set PORT_TX_DW5 */
        val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
        val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
-                 TAP2_DISABLE | TAP3_DISABLE);
+                COEFF_POLARITY | CURSOR_PROGRAM |
+                TAP2_DISABLE | TAP3_DISABLE);
        val |= SCALING_MODE_SEL(0x2);
        val |= RTERM_SELECT(0x6);
        val |= TAP3_DISABLE;