M(CGX_FEATURES_GET,    0x21B, cgx_features_get, msg_req,               \
                               cgx_features_info_msg)                   \
 M(RPM_STATS,           0x21C, rpm_stats, msg_req, rpm_stats_rsp)       \
-M(CGX_MAC_ADDR_RESET,  0x21D, cgx_mac_addr_reset, msg_req, msg_rsp)    \
+M(CGX_MAC_ADDR_RESET,  0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \
+                                                       msg_rsp) \
 M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \
-                              msg_rsp)                                 \
+                                                   cgx_mac_addr_update_rsp) \
 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg,  \
                                 cgx_pfc_rsp)                               \
 /* NPA mbox IDs (range 0x400 - 0x5FF) */                               \
 struct cgx_mac_addr_set_or_get {
        struct mbox_msghdr hdr;
        u8 mac_addr[ETH_ALEN];
+       u32 index;
 };
 
 /* Structure for requesting the operation to
  */
 struct cgx_mac_addr_add_rsp {
        struct mbox_msghdr hdr;
-       u8 index;
+       u32 index;
 };
 
 /* Structure for requesting the operation to
  */
 struct cgx_mac_addr_del_req {
        struct mbox_msghdr hdr;
-       u8 index;
+       u32 index;
 };
 
 /* Structure for response against the operation to
  */
 struct cgx_max_dmac_entries_get_rsp {
        struct mbox_msghdr hdr;
-       u8 max_dmac_filters;
+       u32 max_dmac_filters;
 };
 
 struct cgx_link_user_info {
        int status;
 };
 
+struct cgx_mac_addr_reset_req {
+       struct mbox_msghdr hdr;
+       u32 index;
+};
+
 struct cgx_mac_addr_update_req {
        struct mbox_msghdr hdr;
        u8 mac_addr[ETH_ALEN];
-       u8 index;
+       u32 index;
+};
+
+struct cgx_mac_addr_update_rsp {
+       struct mbox_msghdr hdr;
+       u32 index;
 };
 
 #define RVU_LMAC_FEAT_FC               BIT_ULL(0) /* pause frames */
        LMAC_AF_ERR_PERM_DENIED         = -1103,
        LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED       = -1104,
        LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105,
+       LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108,
+       LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109,
+       LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110,
 };
 
 #endif /* MBOX_H */
 
        return 0;
 }
 
-int rvu_mbox_handler_cgx_mac_addr_reset(struct rvu *rvu, struct msg_req *req,
+int rvu_mbox_handler_cgx_mac_addr_reset(struct rvu *rvu, struct cgx_mac_addr_reset_req *req,
                                        struct msg_rsp *rsp)
 {
        int pf = rvu_get_pf(req->hdr.pcifunc);
 
 int rvu_mbox_handler_cgx_mac_addr_update(struct rvu *rvu,
                                         struct cgx_mac_addr_update_req *req,
-                                        struct msg_rsp *rsp)
+                                        struct cgx_mac_addr_update_rsp *rsp)
 {
        int pf = rvu_get_pf(req->hdr.pcifunc);
        u8 cgx_id, lmac_id;