.altmacro
        .option norelax
 
-ENTRY(__kvm_riscv_switch_to)
+SYM_FUNC_START(__kvm_riscv_switch_to)
        /* Save Host GPRs (except A0 and T0-T6) */
        REG_S   ra, (KVM_ARCH_HOST_RA)(a0)
        REG_S   sp, (KVM_ARCH_HOST_SP)(a0)
 
        /* Return to C code */
        ret
-ENDPROC(__kvm_riscv_switch_to)
+SYM_FUNC_END(__kvm_riscv_switch_to)
 
-ENTRY(__kvm_riscv_unpriv_trap)
+SYM_CODE_START(__kvm_riscv_unpriv_trap)
        /*
         * We assume that faulting unpriv load/store instruction is
         * 4-byte long and blindly increment SEPC by 4.
        csrr    a1, CSR_HTINST
        REG_S   a1, (KVM_ARCH_TRAP_HTINST)(a0)
        sret
-ENDPROC(__kvm_riscv_unpriv_trap)
+SYM_CODE_END(__kvm_riscv_unpriv_trap)
 
 #ifdef CONFIG_FPU
-       .align 3
-       .global __kvm_riscv_fp_f_save
-__kvm_riscv_fp_f_save:
+SYM_FUNC_START(__kvm_riscv_fp_f_save)
        csrr t2, CSR_SSTATUS
        li t1, SR_FS
        csrs CSR_SSTATUS, t1
        sw t0, KVM_ARCH_FP_F_FCSR(a0)
        csrw CSR_SSTATUS, t2
        ret
+SYM_FUNC_END(__kvm_riscv_fp_f_save)
 
-       .align 3
-       .global __kvm_riscv_fp_d_save
-__kvm_riscv_fp_d_save:
+SYM_FUNC_START(__kvm_riscv_fp_d_save)
        csrr t2, CSR_SSTATUS
        li t1, SR_FS
        csrs CSR_SSTATUS, t1
        sw t0, KVM_ARCH_FP_D_FCSR(a0)
        csrw CSR_SSTATUS, t2
        ret
+SYM_FUNC_END(__kvm_riscv_fp_d_save)
 
-       .align 3
-       .global __kvm_riscv_fp_f_restore
-__kvm_riscv_fp_f_restore:
+SYM_FUNC_START(__kvm_riscv_fp_f_restore)
        csrr t2, CSR_SSTATUS
        li t1, SR_FS
        lw t0, KVM_ARCH_FP_F_FCSR(a0)
        fscsr t0
        csrw CSR_SSTATUS, t2
        ret
+SYM_FUNC_END(__kvm_riscv_fp_f_restore)
 
-       .align 3
-       .global __kvm_riscv_fp_d_restore
-__kvm_riscv_fp_d_restore:
+SYM_FUNC_START(__kvm_riscv_fp_d_restore)
        csrr t2, CSR_SSTATUS
        li t1, SR_FS
        lw t0, KVM_ARCH_FP_D_FCSR(a0)
        fscsr t0
        csrw CSR_SSTATUS, t2
        ret
+SYM_FUNC_END(__kvm_riscv_fp_d_restore)
 #endif