struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
        struct hw_perf_event *hwc = &event->hw;
 
-       if (!rvpmu->ctr_get_width)
-       /**
-        * If the pmu driver doesn't support counter width, set it to default
-        * maximum allowed by the specification.
-        */
-               cwidth = 63;
-       else {
-               if (hwc->idx == -1)
-                       /* Handle init case where idx is not initialized yet */
-                       cwidth = rvpmu->ctr_get_width(0);
-               else
-                       cwidth = rvpmu->ctr_get_width(hwc->idx);
-       }
+       if (hwc->idx == -1)
+               /* Handle init case where idx is not initialized yet */
+               cwidth = rvpmu->ctr_get_width(0);
+       else
+               cwidth = rvpmu->ctr_get_width(hwc->idx);
 
        return GENMASK_ULL(cwidth, 0);
 }
 
        return pmu_legacy_ctr_get_idx(event);
 }
 
+/* cycle & instret are always 64 bit, one bit less according to SBI spec */
+static int pmu_legacy_ctr_get_width(int idx)
+{
+       return 63;
+}
+
 static u64 pmu_legacy_read_ctr(struct perf_event *event)
 {
        struct hw_perf_event *hwc = &event->hw;
        pmu->ctr_stop = NULL;
        pmu->event_map = pmu_legacy_event_map;
        pmu->ctr_get_idx = pmu_legacy_ctr_get_idx;
-       pmu->ctr_get_width = NULL;
+       pmu->ctr_get_width = pmu_legacy_ctr_get_width;
        pmu->ctr_clear_idx = NULL;
        pmu->ctr_read = pmu_legacy_read_ctr;
        pmu->event_mapped = pmu_legacy_event_mapped;