arm64: dts: rockchip: Add DP0 for rk3588

The DP0 is compliant with the DisplayPort Specification
Version 1.4, and share the USBDP combo PHY0 with USB 3.1
HOST0 controller.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20250822063959.692098-8-andyshrk@163.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index a18aa1e6c3f1cd92fe26d657bf26784dc1f84127..23a41c151c5deb6e6e3f9410771a6bb593c20609 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1563,6 +1563,36 @@
                };
        };
 
+       dp0: dp@fde50000 {
+               compatible = "rockchip,rk3588-dp";
+               reg = <0x0 0xfde50000 0x0 0x4000>;
+               interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
+               assigned-clocks = <&cru CLK_AUX16M_0>;
+               assigned-clock-rates = <16000000>;
+               clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>,
+                        <&cru CLK_DP0>, <&cru MCLK_I2S4_8CH_TX>,
+                        <&cru MCLK_SPDIF2_DP0>;
+               clock-names = "apb", "aux", "hdcp", "i2s", "spdif";
+               phys = <&usbdp_phy0 PHY_TYPE_DP>;
+               power-domains = <&power RK3588_PD_VO0>;
+               resets = <&cru SRST_DP0>;
+               #sound-dai-cells = <0>;
+               status = "disabled";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       dp0_in: port@0 {
+                               reg = <0>;
+                       };
+
+                       dp0_out: port@1 {
+                               reg = <1>;
+                       };
+               };
+       };
+
        hdmi0: hdmi@fde80000 {
                compatible = "rockchip,rk3588-dw-hdmi-qp";
                reg = <0x0 0xfde80000 0x0 0x20000>;