net/mlx5: Fix wrong address reclaim when command interface is down

[ Upstream commit 1d2bb5ad89f47d8ce8aedc70ef85059ab3870292 ]

When command interface is down, driver to reclaim all 4K page chucks that
were hold by the Firmeware. Fix a bug for 64K page size systems, where
driver repeatedly released only the first chunk of the page.

Define helper function to fill 4K chunks for a given Firmware pages.
Iterate over all unreleased Firmware pages and call the hepler per each.

Fixes: 5adff6a08862 ("net/mlx5: Fix incorrect page count when in internal error")
Signed-off-by: Eran Ben Elisha <eranbe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c b/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c
index e36d3e3675f963c44ff76f6c69a7ac6c72155554..9c3653e06886a679eca755f00f6459b2b4068e8a 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c
@@ -331,6 +331,24 @@ out_free:
        return err;
 }
 
+static u32 fwp_fill_manage_pages_out(struct fw_page *fwp, u32 *out, u32 index,
+                                    u32 npages)
+{
+       u32 pages_set = 0;
+       unsigned int n;
+
+       for_each_clear_bit(n, &fwp->bitmask, MLX5_NUM_4K_IN_PAGE) {
+               MLX5_ARRAY_SET64(manage_pages_out, out, pas, index + pages_set,
+                                fwp->addr + (n * MLX5_ADAPTER_PAGE_SIZE));
+               pages_set++;
+
+               if (!--npages)
+                       break;
+       }
+
+       return pages_set;
+}
+
 static int reclaim_pages_cmd(struct mlx5_core_dev *dev,
                             u32 *in, int in_size, u32 *out, int out_size)
 {
@@ -354,8 +372,7 @@ static int reclaim_pages_cmd(struct mlx5_core_dev *dev,
                if (fwp->func_id != func_id)
                        continue;
 
-               MLX5_ARRAY_SET64(manage_pages_out, out, pas, i, fwp->addr);
-               i++;
+               i += fwp_fill_manage_pages_out(fwp, out, i, npages - i);
        }
 
        MLX5_SET(manage_pages_out, out, output_num_entries, i);