Modifications for 1.1.6:
======================================================================
+* Added MVS1 configuration
+ (Howard Gray, 23 Apr 2002)
+
+* Change rootpath to use ELDK instead of obsolete CDK
+
+* Fix I2C driver on IP860 Board
+
+* Make network retry count configurable; see description for
+ CONFIG_NET_RETRY_COUNT in the README file
+
* Fix flash detection on TQM8260
* Remove dead code from "mkimage"
MIP405 PPC4xx
PIP405 PPC4xx
+Howard Gray <mvsensor@matrix-vision.de>
+
+ MVS1 MPC823
+
-------------------------------------------------------------------------
Unknown / orphaned boards:
ICU862 IP860 IVML24 IVML24_128 \
IVML24_256 IVMS8 IVMS8_128 IVMS8_256 \
LANTEC lwmon MBX MBX860T \
- MHPC NX823 pcu_e RPXClassic \
- RPXlite SM850 SPD823TS SXNI855T \
- TQM823L TQM823L_LCD TQM850L TQM855L \
- TQM860L TQM860L_FEC TTTech \
+ MHPC MVS1 NX823 pcu_e \
+ RPXClassic RPXlite SM850 SPD823TS \
+ SXNI855T TQM823L TQM823L_LCD TQM850L \
+ TQM855L TQM860L TQM860L_FEC TTTech \
"
#########################################################################
echo "BOARD = mhpc" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
+MVS1_config : unconfig
+ @echo "Configuring for $(@:_config=) Board..." ; \
+ cd include ; \
+ echo "ARCH = ppc" > config.mk ; \
+ echo "BOARD = mvs1" >>config.mk ; \
+ echo "CPU = mpc8xx" >>config.mk ; \
+ echo "#include <config_$(@:_config=).h>" >config.h
+
NX823_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd ./include ; \
useful during development since you can try to debug
the conditions that lead to the situation.
+ CONFIG_NET_RETRY_COUNT
+
+ This variable defines the number of retries for
+ network operations like ARP, RARP, TFTP, or BOOTP
+ before giving up the operation. If not defined, a
+ default value of 5 is used.
+
- Command Interpreter:
CFG_HUSH_PARSER
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $^
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+This port is for the MATRIX Vision mvSensor.
+It is an mpc823-based universal image processing board
+with CMOS or CCD sensor, 4MB FLASH and 16-64MB RAM.
+
+See http://www.matrix-vision.de for more details or mail...
+
+mvsensor@matrix-vision.de
+
+Howard Gray
+MATRIX Vision GmbH
+Talstr. 16
+D-71570
+Oppenweiler
+Germany
+
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# TQM8xxL boards
+#
+
+TEXT_BASE = 0x40000000
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Changes for MATRIX Vision MVsensor (C) Copyright 2001
+ * MATRIX Vision GmbH / hg, info@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc8xx.h>
+
+#undef MVDEBUG
+#ifdef MVDEBUG
+#define mvdebug debug
+#else
+#define mvdebug(p) do {} while (0)
+#endif
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+
+#ifdef CONFIG_MVS_16BIT_FLASH
+ #define FLASH_DATA_MASK 0xffff
+ #define FLASH_SHIFT 0
+#else
+ #define FLASH_DATA_MASK 0xffffffff
+ #define FLASH_SHIFT 1
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *address, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ unsigned long size_b0, size_b1;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+#if defined (FLASH_BASE1_PRELIM)
+ size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+ if (size_b1 > size_b0) {
+ printf ("## ERROR: "
+ "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+ size_b1, size_b1<<20,
+ size_b0, size_b0<<20
+ );
+ flash_info[0].flash_id = FLASH_UNKNOWN;
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[0].sector_count = -1;
+ flash_info[1].sector_count = -1;
+ flash_info[0].size = 0;
+ flash_info[1].size = 0;
+ return (0);
+ }
+#else
+ size_b1 = 0;
+#endif
+
+ /* Remap FLASH according to real size */
+ memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+#ifdef CONFIG_MVS_16BIT_FLASH
+ memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
+#else
+ memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_GPCM | BR_V;
+#endif
+
+ /* Re-do sizing to get full correct info */
+ size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ &flash_info[0]);
+
+ if (size_b1) {
+ memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+#ifdef CONFIG_MVS_16BIT_FLASH
+ memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+ BR_PS_16 | BR_MS_GPCM | BR_V;
+#else
+ memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+ BR_PS_32 | BR_MS_GPCM | BR_V;
+#endif
+ /* Re-do sizing to get full correct info */
+ size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+ &flash_info[1]);
+
+ flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ &flash_info[1]);
+ } else {
+ memctl->memc_br1 = 0; /* invalidate bank */
+
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[1].sector_count = -1;
+ }
+
+ flash_info[0].size = size_b0;
+ flash_info[1].size = size_b1;
+
+ return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+
+ /* set up sector start address table */
+ if (info->flash_id & FLASH_BTYPE)
+ { /* bottom boot sector types - these are the useful ones! */
+ /* set sector offsets for bottom boot block type */
+ if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B)
+ { // AMDLV320B has 8 x 8k bottom boot sectors */
+ for (i = 0; i < 8; i++) /* +8k */
+ info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT));
+ for (; i < info->sector_count; i++) /* +64k */
+ info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00070000 << FLASH_SHIFT);
+ }
+ else
+ { /* other types have 4 bottom boot sectors (16,8,8,32) */
+ i = 0;
+ info->start[i++] = base + 0x00000000; /* - */
+ info->start[i++] = base + (0x00004000 << FLASH_SHIFT); /* +16k */
+ info->start[i++] = base + (0x00006000 << FLASH_SHIFT); /* +8k */
+ info->start[i++] = base + (0x00008000 << FLASH_SHIFT); /* +8k */
+ info->start[i++] = base + (0x00010000 << FLASH_SHIFT); /* +32k */
+ for (; i < info->sector_count; i++) /* +64k */
+ info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00030000 << FLASH_SHIFT);
+ }
+ }
+ else
+ { /* top boot sector types - not so useful */
+ /* set sector offsets for top boot block type */
+ if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T)
+ { // AMDLV320T has 8 x 8k top boot sectors */
+ for (i = 0; i < info->sector_count - 8; i++) /* +64k */
+ info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT));
+ for (; i < info->sector_count; i++) /* +8k */
+ info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT));
+ }
+ else
+ { /* other types have 4 top boot sectors (32,8,8,16) */
+ for (i = 0; i < info->sector_count - 4; i++) /* +64k */
+ info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT));
+
+ info->start[i++] = base + info->size - (0x00010000 << FLASH_SHIFT); /* -32k */
+ info->start[i++] = base + info->size - (0x00008000 << FLASH_SHIFT); /* -8k */
+ info->start[i++] = base + info->size - (0x00006000 << FLASH_SHIFT); /* -8k */
+ info->start[i] = base + info->size - (0x00004000 << FLASH_SHIFT); /* -16k */
+ }
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
+ case FLASH_MAN_STM: printf ("ST "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_STMW320DB: printf ("M29W320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_STMW320DT: printf ("M29W320T (32 Mbit, top boot sector)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+#define AMD_ID_LV160T_MVS (AMD_ID_LV160T & FLASH_DATA_MASK)
+#define AMD_ID_LV160B_MVS (AMD_ID_LV160B & FLASH_DATA_MASK)
+#define AMD_ID_LV320T_MVS (AMD_ID_LV320T & FLASH_DATA_MASK)
+#define AMD_ID_LV320B_MVS (AMD_ID_LV320B & FLASH_DATA_MASK)
+#define STM_ID_W320DT_MVS (STM_ID_29W320DT & FLASH_DATA_MASK)
+#define STM_ID_W320DB_MVS (STM_ID_29W320DB & FLASH_DATA_MASK)
+#define AMD_MANUFACT_MVS (AMD_MANUFACT & FLASH_DATA_MASK)
+#define FUJ_MANUFACT_MVS (FUJ_MANUFACT & FLASH_DATA_MASK)
+#define STM_MANUFACT_MVS (STM_MANUFACT & FLASH_DATA_MASK)
+
+#define AUTOSELECT_ADDR1 0x0555
+#define AUTOSELECT_ADDR2 0x02AA
+#define AUTOSELECT_ADDR3 AUTOSELECT_ADDR1
+
+#define AUTOSELECT_DATA1 (0x00AA00AA & FLASH_DATA_MASK)
+#define AUTOSELECT_DATA2 (0x00550055 & FLASH_DATA_MASK)
+#define AUTOSELECT_DATA3 (0x00900090 & FLASH_DATA_MASK)
+
+#define RESET_BANK_DATA (0x00F000F0 & FLASH_DATA_MASK)
+
+static ulong flash_get_size (vu_long *address, flash_info_t *info)
+{
+ short i;
+#ifdef CONFIG_MVS_16BIT_FLASH
+ ushort value;
+ vu_short *addr = (vu_short *)address;
+#else
+ ulong value;
+ vu_long *addr = (vu_long *)address;
+#endif
+ ulong base = (ulong)address;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr[AUTOSELECT_ADDR1] = AUTOSELECT_DATA1;
+ addr[AUTOSELECT_ADDR2] = AUTOSELECT_DATA2;
+ addr[AUTOSELECT_ADDR3] = AUTOSELECT_DATA3;
+
+ value = addr[0]; /* manufacturer ID */
+ switch (value) {
+ case AMD_MANUFACT_MVS:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case FUJ_MANUFACT_MVS:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case STM_MANUFACT_MVS:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr[1]; /* device ID */
+ switch (value) {
+ case AMD_ID_LV160T_MVS:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 37;
+ info->size = (0x00200000 << FLASH_SHIFT);
+ break; /* => 2 or 4 MB */
+
+ case AMD_ID_LV160B_MVS:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 37;
+ info->size = (0x00200000 << FLASH_SHIFT);
+ break; /* => 2 or 4 MB */
+
+ case AMD_ID_LV320T_MVS:
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 71;
+ info->size = (0x00400000 << FLASH_SHIFT);
+ break; /* => 4 or 8 MB */
+
+ case AMD_ID_LV320B_MVS:
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 71;
+ info->size = (0x00400000 << FLASH_SHIFT);
+ break; /* => 4 or 8MB */
+
+ case STM_ID_W320DT_MVS:
+ info->flash_id += FLASH_STMW320DT;
+ info->sector_count = 67;
+ info->size = (0x00400000 << FLASH_SHIFT);
+ break; /* => 4 or 8 MB */
+
+ case STM_ID_W320DB_MVS:
+ info->flash_id += FLASH_STMW320DB;
+ info->sector_count = 67;
+ info->size = (0x00400000 << FLASH_SHIFT);
+ break; /* => 4 or 8MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ /* set up sector start address table */
+ flash_get_offsets (base, info);
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+#ifdef CONFIG_MVS_16BIT_FLASH
+ addr = (vu_short *)(info->start[i]);
+#else
+ addr = (vu_long *)(info->start[i]);
+#endif
+ info->protect[i] = addr[2] & 1;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+#ifdef CONFIG_MVS_16BIT_FLASH
+ addr = (vu_short *)info->start[0];
+#else
+ addr = (vu_long *)info->start[0];
+#endif
+ *addr = RESET_BANK_DATA; /* reset bank */
+ }
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+#define ERASE_ADDR1 0x0555
+#define ERASE_ADDR2 0x02AA
+#define ERASE_ADDR3 ERASE_ADDR1
+#define ERASE_ADDR4 ERASE_ADDR1
+#define ERASE_ADDR5 ERASE_ADDR2
+
+#define ERASE_DATA1 (0x00AA00AA & FLASH_DATA_MASK)
+#define ERASE_DATA2 (0x00550055 & FLASH_DATA_MASK)
+#define ERASE_DATA3 (0x00800080 & FLASH_DATA_MASK)
+#define ERASE_DATA4 ERASE_DATA1
+#define ERASE_DATA5 ERASE_DATA2
+
+#define ERASE_SECTOR_DATA (0x00300030 & FLASH_DATA_MASK)
+#define ERASE_CHIP_DATA (0x00100010 & FLASH_DATA_MASK)
+#define ERASE_CONFIRM_DATA (0x00800080 & FLASH_DATA_MASK)
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+#ifdef CONFIG_MVS_16BIT_FLASH
+ vu_short *addr = (vu_short *)(info->start[0]);
+#else
+ vu_long *addr = (vu_long *)(info->start[0]);
+#endif
+ int flag, prot, sect, l_sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if ((info->flash_id == FLASH_UNKNOWN) ||
+ (info->flash_id > FLASH_AMD_COMP)) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr[ERASE_ADDR1] = ERASE_DATA1;
+ addr[ERASE_ADDR2] = ERASE_DATA2;
+ addr[ERASE_ADDR3] = ERASE_DATA3;
+ addr[ERASE_ADDR4] = ERASE_DATA4;
+ addr[ERASE_ADDR5] = ERASE_DATA5;
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+#ifdef CONFIG_MVS_16BIT_FLASH
+ addr = (vu_short *)(info->start[sect]);
+#else
+ addr = (vu_long *)(info->start[sect]);
+#endif
+ addr[0] = ERASE_SECTOR_DATA;
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+
+ start = get_timer (0);
+ last = start;
+#ifdef CONFIG_MVS_16BIT_FLASH
+ addr = (vu_short *)(info->start[l_sect]);
+#else
+ addr = (vu_long *)(info->start[l_sect]);
+#endif
+ while ((addr[0] & ERASE_CONFIRM_DATA) != ERASE_CONFIRM_DATA) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+DONE:
+ /* reset to read mode */
+#ifdef CONFIG_MVS_16BIT_FLASH
+ addr = (vu_short *)info->start[0];
+#else
+ addr = (vu_long *)info->start[0];
+#endif
+ addr[0] = RESET_BANK_DATA; /* reset bank */
+
+ printf (" done\n");
+ return 0;
+}
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+#define BUFF_INC 4
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ mvdebug (("+write_buff %p ==> 0x%08lx, count = 0x%08lx\n", src, addr, cnt));
+
+ wp = (addr & ~3); /* get lower word aligned address */
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ mvdebug ((" handle unaligned start bytes (cnt = 0x%08%lx)\n", cnt));
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<BUFF_INC && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<BUFF_INC; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += BUFF_INC;
+ }
+
+ /*
+ * handle (half)word aligned part
+ */
+ mvdebug ((" handle word aligned part (cnt = 0x%08%lx)\n", cnt));
+ while (cnt >= BUFF_INC) {
+ data = 0;
+ for (i=0; i<BUFF_INC; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += BUFF_INC;
+ cnt -= BUFF_INC;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ mvdebug ((" handle unaligned tail bytes (cnt = 0x%08%lx)\n", cnt));
+ data = 0;
+ for (i=0, cp=wp; i<BUFF_INC && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<BUFF_INC; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+#define WRITE_ADDR1 0x0555
+#define WRITE_ADDR2 0x02AA
+#define WRITE_ADDR3 WRITE_ADDR1
+
+#define WRITE_DATA1 (0x00AA00AA & FLASH_DATA_MASK)
+#define WRITE_DATA2 (0x00550055 & FLASH_DATA_MASK)
+#define WRITE_DATA3 (0x00A000A0 & FLASH_DATA_MASK)
+
+#define WRITE_CONFIRM_DATA ERASE_CONFIRM_DATA
+
+#ifndef CONFIG_MVS_16BIT_FLASH
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ vu_long *addr = (vu_long *)(info->start[0]);
+ ulong start;
+ int flag;
+
+ mvdebug (("+write_word (to 0x%08lx)\n", dest));
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr[WRITE_ADDR1] = WRITE_DATA1;
+ addr[WRITE_ADDR2] = WRITE_DATA2;
+ addr[WRITE_ADDR3] = WRITE_DATA3;
+
+ *((vu_long *)dest) = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ addr = (vu_long *)dest;
+ while ((*addr & WRITE_CONFIRM_DATA) != (data & WRITE_CONFIRM_DATA)) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+
+ mvdebug (("-write_word\n"));
+ return (0);
+}
+#else // CONFIG_MVS_16BIT_FLASH
+/*-----------------------------------------------------------------------
+ * Write a halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_halfword (flash_info_t *info, ulong dest, ushort data)
+{
+ vu_short *addr = (vu_short *)(info->start[0]);
+ ulong start;
+ int flag;
+
+ mvdebug (("+write_halfword (to 0x%08lx)\n", dest));
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_short *)dest) & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr[WRITE_ADDR1] = WRITE_DATA1;
+ addr[WRITE_ADDR2] = WRITE_DATA2;
+ addr[WRITE_ADDR3] = WRITE_DATA3;
+
+ *((vu_short *)dest) = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ addr = (vu_short *)dest;
+ while ((*addr & WRITE_CONFIRM_DATA) != (data & WRITE_CONFIRM_DATA)) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ mvdebug (("-write_halfword\n"));
+ return (0);
+}
+
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ int result = 0;
+
+ if (write_halfword (info, dest, (data & ~FLASH_DATA_MASK) >> 16) == 0)
+ {
+ dest += 2;
+ data = data & FLASH_DATA_MASK;
+ result = write_halfword (info, dest, data);
+ }
+ return result;
+}
+#endif
+/*-----------------------------------------------------------------------
+ */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Changes for MATRIX Vision MVsensor (C) Copyright 2001
+ * MATRIX Vision GmbH / hg, info@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include "mpc8xx.h"
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define _NOT_USED_ 0xFFFFFFFF
+
+const uint sdram_table[] =
+{
+ /*
+ * Single Read. (Offset 0 in UPMA RAM)
+ */
+ 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
+ 0x1FF5FC47, /* last */
+ /*
+ * SDRAM Initialization (offset 5 in UPMA RAM)
+ *
+ * This is no UPM entry point. The following definition uses
+ * the remaining space to establish an initialization
+ * sequence, which is executed by a RUN command.
+ *
+ */
+ 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
+ /*
+ * Burst Read. (Offset 8 in UPMA RAM)
+ */
+ 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
+ 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Single Write. (Offset 18 in UPMA RAM)
+ */
+ 0x1F0DFC04 /*0x1F2DFC04??*/, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Burst Write. (Offset 20 in UPMA RAM)
+ */
+ 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
+ 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Refresh (Offset 30 in UPMA RAM)
+ */
+ 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+ 0xFFFFFC84, 0xFFFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Exception. (Offset 3c in UPMA RAM)
+ */
+ 0x7FFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Test TQ ID string (TQM8xx...)
+ * If present, check for "L" type (no second DRAM bank),
+ * otherwise "L" type is assumed as default.
+ *
+ * Return 1 for "L" type, 0 else.
+ */
+
+int checkboard (void)
+{
+ printf ("MATRIX Vision MVsensor\n");
+ return 1;
+}
+
+
+
+#ifdef DO_RAM_TEST
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Test SDRAM by writing its address to itself and reading several times
+*/
+#define READ_RUNS 4
+static void test_dram (unsigned long *start, unsigned long *end)
+{
+ unsigned long *addr;
+ unsigned long value;
+ int read_runs, errors, addr_errors;
+
+ printf ("\nChecking SDRAM from %p to %p\n", start, end);
+ udelay(1000000);
+ for (addr = start; addr < end; addr++)
+ *addr = (unsigned long)addr;
+
+ for (addr = start, addr_errors = 0; addr < end; addr++)
+ {
+ for (read_runs = READ_RUNS, errors = 0;
+ read_runs > 0; read_runs--)
+ {
+ if ((value = *addr) != (unsigned long)addr)
+ errors++;
+ }
+ if (errors > 0)
+ {
+ addr_errors++;
+ printf ("SDRAM errors (%d) at %p, last read = %ld\n",
+ errors, addr, value);
+ udelay(10000);
+ }
+ }
+ printf ("SDRAM check finished, total errors = %d\n", addr_errors);
+}
+#endif // DO_RAM_TEST
+
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ long int size_b0, size_b1, size8, size9;
+
+ upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+ /*
+ * Preliminary prescaler for refresh (depends on number of
+ * banks): This value is selected for four cycles every 62.4 us
+ * with two SDRAM banks or four cycles every 31.2 us with one
+ * bank. It will be adjusted after memory sizing.
+ */
+ memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+
+ memctl->memc_mar = 0x00000088;
+
+ /*
+ * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
+ * preliminary addresses - these have to be modified after the
+ * SDRAM size has been determined.
+ */
+ memctl->memc_or2 = CFG_OR2_PRELIM;
+ memctl->memc_br2 = CFG_BR2_PRELIM;
+
+#if defined (CFG_OR3_PRELIM) && defined (CFG_BR3_PRELIM)
+ if (board_type == 0) { /* "L" type boards have only one bank SDRAM */
+ memctl->memc_or3 = CFG_OR3_PRELIM;
+ memctl->memc_br3 = CFG_BR3_PRELIM;
+ }
+#endif
+
+ memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
+
+ udelay(200);
+
+ /* perform SDRAM initializsation sequence */
+
+ memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
+ udelay(1);
+ memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
+ udelay(1);
+
+ if (board_type == 0) { /* "L" type boards have only one bank SDRAM */
+ memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
+ udelay(1);
+ memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
+ udelay(1);
+ }
+
+ memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
+
+ udelay (1000);
+
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ *
+ * try 8 column mode
+ */
+ size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+
+ udelay (1000);
+ /*
+ * try 9 column mode
+ */
+ size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+
+ if (size8 < size9) { /* leave configuration at 9 columns */
+ size_b0 = size9;
+ } else { /* back to 8 columns */
+ size_b0 = size8;
+ memctl->memc_mamr = CFG_MAMR_8COL;
+ udelay(500);
+ }
+
+ if (board_type == 0) { /* "L" type boards have only one bank SDRAM */
+ /*
+ * Check Bank 1 Memory Size
+ * use current column settings
+ * [9 column SDRAM may also be used in 8 column mode,
+ * but then only half the real size will be used.]
+ */
+#if defined (SDRAM_BASE3_PRELIM)
+ size_b1 = dram_size (memctl->memc_mamr, (ulong *)SDRAM_BASE3_PRELIM,
+ SDRAM_MAX_SIZE);
+#else
+ size_b1 = 0;
+#endif
+ } else {
+ size_b1 = 0;
+ }
+
+ udelay (1000);
+
+ /*
+ * Adjust refresh rate depending on SDRAM type, both banks
+ * For types > 128 MBit leave it at the current (fast) rate
+ */
+ if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
+ /* reduce to 15.6 us (62.4 us / quad) */
+ memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+ udelay(1000);
+ }
+
+ /*
+ * Final mapping: map bigger bank first
+ */
+ if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
+
+ memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+ memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+ if (size_b0 > 0) {
+ /*
+ * Position Bank 0 immediately above Bank 1
+ */
+ memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+ memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+ + size_b1;
+ } else {
+ unsigned long reg;
+ /*
+ * No bank 0
+ *
+ * invalidate bank
+ */
+ memctl->memc_br2 = 0;
+
+ /* adjust refresh rate depending on SDRAM type, one bank */
+ reg = memctl->memc_mptpr;
+ reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
+ memctl->memc_mptpr = reg;
+ }
+
+ } else { /* SDRAM Bank 0 is bigger - map first */
+
+ memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+ memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+ if (size_b1 > 0) {
+ /*
+ * Position Bank 1 immediately above Bank 0
+ */
+ memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+ memctl->memc_br3 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+ + size_b0;
+ } else {
+ unsigned long reg;
+ /*
+ * No bank 1
+ *
+ * invalidate bank
+ */
+ memctl->memc_br3 = 0;
+
+ /* adjust refresh rate depending on SDRAM type, one bank */
+ reg = memctl->memc_mptpr;
+ reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
+ memctl->memc_mptpr = reg;
+ }
+ }
+
+ udelay(10000);
+
+#ifdef DO_RAM_TEST
+ if (size_b0 > 0)
+ test_dram ((unsigned long *)CFG_SDRAM_BASE,
+ (unsigned long *)(CFG_SDRAM_BASE + size_b0));
+#endif
+
+ return (size_b0 + size_b1);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ volatile long int *addr;
+ long int cnt, val;
+
+
+ memctl->memc_mamr = mamr_value;
+
+ for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ *addr = ~cnt;
+ }
+
+ /* write 0 to base address */
+ addr = base;
+ *addr = 0;
+
+ /* check at base address */
+ if ((val = *addr) != 0) {
+ return (0);
+ }
+
+ for (cnt = 1; ; cnt <<= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ val = *addr;
+
+ if (val != (~cnt)) {
+ return (cnt * sizeof(long));
+ }
+ }
+ /* NOTREACHED */
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+u8 *dhcp_vendorex_prep(u8 *e)
+{
+char *ptr;
+
+/* DHCP vendor-class-identifier = 60 */
+ if ((ptr = getenv("dhcp_vendor-class-identifier")))
+ {
+ *e++ = 60;
+ *e++ = strlen(ptr);
+ while (*ptr)
+ *e++ = *ptr++;
+ }
+/* my DHCP_CLIENT_IDENTIFIER = 61 */
+ if ((ptr = getenv("dhcp_client_id")))
+ {
+ *e++ = 61;
+ *e++ = strlen(ptr);
+ while (*ptr)
+ *e++ = *ptr++;
+ }
+
+ return e;
+}
+
+
+/* ------------------------------------------------------------------------- */
+u8 *dhcp_vendorex_proc(u8 *popt)
+{
+ return NULL;
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
+ ppc/ppcstring.o (.text)
+ ppc/vsprintf.o (.text)
+ ppc/crc32.o (.text)
+ ppc/zlib.o (.text)
+
+ ppc/ctype.o (.text)
+ ppc/extable.o (.text)
+ ppc/ldiv.o (.text)
+ ppc/kgdb.o (.text)
+ ppc/string.o (.text)
+ ppc/ticks.o (.text)
+ ppc/time.o (.text)
+ /*
+ ppc/display_options.o (.text)
+ */
+
+ . = env_offset;
+ common/environment.o(.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
+ ppc/vsprintf.o (.text)
+ ppc/crc32.o (.text)
+
+ . = env_offset;
+ common/environment.o(.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
return rcode;
}
-#elif CFG_ENV_IS_IN_EEPROM
+#elif defined(CFG_ENV_IS_IN_EEPROM)
#define NVRAM_SAVESTR SAVESTR(EEPROM)
int saveenv(void)
#endif /* CONFIG_SXNI855T */
-/*** TQM823L, TQM850L, ETX094 ***************************************/
+/*** MVS1, TQM823L, TQM850L, ETX094 ********************************/
-#if defined(CONFIG_TQM823L) || \
+#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
+ defined(CONFIG_TQM823L) || \
defined(CONFIG_TQM850L) || \
defined(CONFIG_ETX094) || \
(defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
*/
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002600)
-#endif /* CONFIG_TQM823L, CONFIG_TQM850L, CONFIG_ETX094, CONFIG_LANTEC v1 */
+#endif /* CONFIG_MVS v1, CONFIG_TQM823L, CONFIG_TQM850L, CONFIG_ETX094, CONFIG_LANTEC v1 */
/*** TQM860L, TQM855L ************************************************/
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/LinuxPPC " \
+ "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
"nfsaddrs=10.0.0.99:10.0.0.2"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_ENV_IS_IN_FLASH
#undef CFG_ENV_IS_IN_NVRAM
-#define CFG_ENV_IS_IN_NVRAM
-#define DEBUG_I2C
-#undef CFG_ENV_IS_IN_EEPROM
+#undef CFG_ENV_IS_IN_NVRAM
+#undef DEBUG_I2C
+#define CFG_ENV_IS_IN_EEPROM
#ifdef CFG_ENV_IS_IN_NVRAM
#define CFG_ENV_ADDR 0x20000000 /* use SRAM */
#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/LinuxPPC " \
+ "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
"nfsaddrs=10.0.0.99:10.0.0.2"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/LinuxPPC " \
+ "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
"nfsaddrs=10.0.0.99:10.0.0.2"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_BOOTCOMMAND "bootm 20000" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/LinuxPPC " \
+ "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
"nfsaddrs=10.0.0.99:10.0.0.2"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
+#define CONFIG_MVS 1 /* ...on a MVsensor module */
+#define CONFIG_MVS_16BIT_FLASH /* ...with 16-bit flash access */
+#define CONFIG_8xx_GCLK_FREQ 50000000/* ... and a 50 MHz CPU */
+
+#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
+
+#undef CONFIG_8xx_CONS_SMC1 /* Console is *NOT* on SMC1 */
+#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
+#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE 115200 /* console baudrate */
+#define CONFIG_BOOTDELAY 5 /* autoboot after this many seconds */
+
+#define CONFIG_PREBOOT "echo;echo To mount root over NFS use \"run bootnet\";echo To mount root from FLASH use \"run bootflash\";echo"
+#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw"
+#define CONFIG_BOOTCOMMAND \
+ "bootp; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "bootm"
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+
+#define CONFIG_WATCHDOG /* watchdog disabled/enabled */
+
+#undef CONFIG_STATUS_LED /* Status LED disabled/enabled */
+
+#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_VENDOREX )
+
+#undef CONFIG_MAC_PARTITION
+#undef CONFIG_DOS_PARTITION
+
+#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
+
+/* MVsensor uses a really minimal PPCBoot ! */
+#define CONFIG_COMMANDS (CFG_CMD_LOADS | \
+ CFG_CMD_LOADB | \
+ CFG_CMD_IMI | \
+ CFG_CMD_FLASH | \
+ CFG_CMD_MEMORY | \
+ CFG_CMD_NET | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_ENV | \
+ CFG_CMD_BOOTD | \
+ CFG_CMD_RUN )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#undef CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#undef CFG_HUSH_PARSER /* Hush parse for ppcboot ?? */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0x40000000
+
+#define CFG_MONITOR_LEN (128 << 10) /* Reserve 192 kB for Monitor */
+
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip (for AMD320DB chip) */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_ENV_IS_IN_FLASH 1
+
+/* 4MB flash - use bottom sectors of a bottom boot sector flash (16 bit access) */
+#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector (bottom boot sector) */
+#define CFG_ENV_SIZE 0x2000 /* Used Size of Environment Sector 8k */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ */
+#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK SCCR_EBDF11
+#define CFG_SCCR (SCCR_TBS | \
+ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR (0xEC000000)
+#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PCCARD 0 /* **DON'T** Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+#undef CONFIG_IDE_RESET /* reset for ide not supported */
+
+#define CFG_IDE_MAXBUS 0 /* max. no. of IDE buses */
+#define CFG_IDE_MAXDEVICE 0 /* max. no. of drives per IDE bus */
+
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET 0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define CFG_DER 0x2002000F*/
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
+#undef FLASH_BASE1_PRELIM
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
+
+
+/*
+ * FLASH timing:
+ */
+/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
+ OR_SCY_2_CLK | OR_EHTR | OR_BI)
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
+/*
+#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
+ OR_SCY_5_CLK | OR_EHTR)
+*/
+
+#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#ifdef CONFIG_MVS_16BIT_FLASH
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#else
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
+#endif
+
+#undef CFG_OR1_REMAP
+#undef CFG_OR1_PRELIM
+#undef CFG_BR1_PRELIM
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
+#undef SDRAM_BASE3_PRELIM
+#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
+#define CFG_OR_TIMING_SDRAM 0x00000A00
+
+#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#undef CFG_OR3_PRELIM
+#undef CFG_BR3_PRELIM
+
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ * gclk CPU clock (not bus clock!)
+ * Trefresh Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096 Rows from SDRAM example configuration
+ * 1000 factor s -> ms
+ * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4 Number of refresh cycles per period
+ * 64 Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider = 98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+#define CFG_MAMR_PTA 98
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
+#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
+#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
+#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
+#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A7 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#endif /* __CONFIG_H */
#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/LinuxPPC " \
+ "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
"nfsaddrs=10.0.0.99:10.0.0.2"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
/* 8 64K x 8 uniform sectors */
#define STM_ID_x800AB 0x005B005B /* M29W800AB ID (8M = 512K x 16 ) */
+#define STM_ID_29W320DT 0x22CA22CA /* M29W320DT ID (32 M, top boot sector) */
+#define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect) */
#define STM_ID_29W040B 0x00E300E3 /* M29W040B ID (4M = 512K x 8) */
#define INTEL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */
#define FLASH_SST160A 0x0046 /* SST 39xF160A ID ( 16M = 1M x 16 ) */
#define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */
+#define FLASH_STMW320DT 0x0052 /* STM M29W320DT (32 M, top boot sector) */
+#define FLASH_STMW320DB 0x0053 /* STM M29W320DB (32 M, bottom boot sect)*/
#define FLASH_STM320DB 0x00CB /* STM M29W320DB (4M = 64K x 64, bottom)*/
#define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */
#define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+/***** MVS v1 **********************************************************/
+#elif (defined(CONFIG_MVS) && CONFIG_MVS < 2)
+# define STATUS_LED_PAR im_ioport.iop_pdpar
+# define STATUS_LED_DIR im_ioport.iop_pddir
+# undef STATUS_LED_ODR
+# define STATUS_LED_DAT im_ioport.iop_pddat
+
+# define STATUS_LED_BIT 0x00000001
+# define STATUS_LED_PERIOD (CFG_HZ / 2)
+# define STATUS_LED_STATE STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
+
+# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+
/***** ETX_094 ********************************************************/
#elif defined(CONFIG_ETX094)
#if (CONFIG_COMMANDS & CFG_CMD_NET)
#define TIMEOUT 5 /* Seconds before trying ARP again */
-#define TIMEOUT_COUNT 1 /* # of timeouts before giving up */
+#ifndef CONFIG_NET_RETRY_COUNT
+# define TIMEOUT_COUNT 5 /* # of timeouts before giving up */
+#else
+# define TIMEOUT_COUNT (CONFIG_NET_RETRY_COUNT)
+#endif
static void ArpHandler(uchar *pkt, unsigned dest, unsigned src, unsigned len);
static void ArpTimeout(void);
#if (CONFIG_COMMANDS & CFG_CMD_NET)
#define TIMEOUT 5 /* Seconds before trying BOOTP again */
-#define TIMEOUT_COUNT 1 /* # of timeouts before giving up */
+#ifndef CONFIG_NET_RETRY_COUNT
+# define TIMEOUT_COUNT 5 /* # of timeouts before giving up */
+#else
+# define TIMEOUT_COUNT (CONFIG_NET_RETRY_COUNT)
+#endif
#define PORT_BOOTPS 67 /* BOOTP server UDP port */
#define PORT_BOOTPC 68 /* BOOTP client UDP port */
#if (CONFIG_COMMANDS & CFG_CMD_NET)
#define TIMEOUT 5 /* Seconds before trying BOOTP again */
-#define TIMEOUT_COUNT 1 /* # of timeouts before giving up */
+#ifndef CONFIG_NET_RETRY_COUNT
+# define TIMEOUT_COUNT 5 /* # of timeouts before giving up */
+#else
+# define TIMEOUT_COUNT (CONFIG_NET_RETRY_COUNT)
+#endif
int RarpTry;
#define WELL_KNOWN_PORT 69 /* Well known TFTP port # */
#define TIMEOUT 2 /* Seconds to timeout for a lost pkt */
-#define TIMEOUT_COUNT 10 /* # of timeouts before giving up */
+#ifndef CONFIG_NET_RETRY_COUNT
+# define TIMEOUT_COUNT 10 /* # of timeouts before giving up */
+#else
+# define TIMEOUT_COUNT (CONFIG_NET_RETRY_COUNT * 2)
+#endif
/* (for checking the image size) */
#define HASHES_PER_LINE 65 /* Number of "loading" hashes per line */
projects / users / rw / ppcboot.git / commitdiff