@end deffn
@deffn {Flash Driver} {stm32l4x}
-All members of the STM32 G0, G4, L4, L4+, L5, U5, WB and WL
+All members of the STM32 G0, G4, L4, L4+, L5, U0, U5, WB and WL
microcontroller families from STMicroelectronics include internal flash
and use ARM Cortex-M0+, M4 and M33 cores.
The driver automatically recognizes a number of these chips using
* http://www.st.com/resource/en/reference_manual/dm00346336.pdf
*/
+/* STM32U0xxx series for reference.
+ *
+ * RM0503 (STM32U0xx)
+ * https://www.st.com/resource/en/reference_manual/rm0503-stm32u0-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
+ */
+
/* STM32U5xxx series for reference.
*
* RM0456 (STM32U5xx)
};
/* human readable list of families this drivers supports (sorted alphabetically) */
-static const char *device_families = "STM32C0/G0/G4/L4/L4+/L5/U5/WB/WL";
+static const char *device_families = "STM32C0/G0/G4/L4/L4+/L5/U0/U5/WB/WL";
static const struct stm32l4_rev stm32l47_l48xx_revs[] = {
{ 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
{ 0x1000, "A" },
};
+static const struct stm32l4_rev stm32u0xx_revs[] = {
+ { 0x1000, "A" },
+};
+
static const struct stm32l4_rev stm32g43_g44xx_revs[] = {
{ 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
};
.otp_base = 0x1FFF7000,
.otp_size = 1024,
},
+ {
+ .id = DEVID_STM32U031XX,
+ .revs = stm32u0xx_revs,
+ .num_revs = ARRAY_SIZE(stm32u0xx_revs),
+ .device_str = "STM32U031xx",
+ .max_flash_size_kb = 64,
+ .flags = F_NONE,
+ .flash_regs_base = 0x40022000,
+ .fsize_addr = 0x1FFF3EA0,
+ .otp_base = 0x1FFF6800,
+ .otp_size = 1024,
+ },
+ {
+ .id = DEVID_STM32U073_U083XX,
+ .revs = stm32u0xx_revs,
+ .num_revs = ARRAY_SIZE(stm32u0xx_revs),
+ .device_str = "STM32U073/U083xx",
+ .max_flash_size_kb = 256,
+ .flags = F_NONE,
+ .flash_regs_base = 0x40022000,
+ .fsize_addr = 0x1FFF6EA0,
+ .otp_base = 0x1FFF6800,
+ .otp_size = 1024,
+ },
{
.id = DEVID_STM32U59_U5AXX,
.revs = stm32u59_u5axx_revs,
case DEVID_STM32C03XX:
case DEVID_STM32G05_G06XX:
case DEVID_STM32G07_G08XX:
+ case DEVID_STM32U031XX:
+ case DEVID_STM32U073_U083XX:
case DEVID_STM32L45_L46XX:
case DEVID_STM32L41_L42XX:
case DEVID_STM32G03_G04XX:
#define DEVID_STM32C03XX 0x453
#define DEVID_STM32U53_U54XX 0x455
#define DEVID_STM32G05_G06XX 0x456
+#define DEVID_STM32U031XX 0x459
#define DEVID_STM32G07_G08XX 0x460
#define DEVID_STM32L49_L4AXX 0x461
#define DEVID_STM32L45_L46XX 0x462
#define DEVID_STM32G49_G4AXX 0x479
#define DEVID_STM32U59_U5AXX 0x481
#define DEVID_STM32U57_U58XX 0x482
+#define DEVID_STM32U073_U083XX 0x489
#define DEVID_STM32WBA5X 0x492
#define DEVID_STM32WB1XX 0x494
#define DEVID_STM32WB5XX 0x495