drm/i915/skl: Rework MOCS tables to keep common part in a define

The MOCS tables are going to be very similar across platforms.

To reduce the amount of copied code, this patch rips the common part and
puts it into a definition valid for all gen9 platforms.

v2: Made defines for or-ing flags. Renamed macros from MOCS_TABLE
    to MOCS_ENTRIES. (Joonas)
v3 (Lucas):
  - Fix indentation
  - Rebase on rework done by additional patch
  - Remove define for or-ing flags as it made the table more complex by
    requiring zeroed values to be passed
  - Do not embed comma in the macro, so to treat that just as another
    item and please source code formatting tools

Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190124000604.18861-4-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 4ea80bb7dcc8ca9116285f3d5461a437aae72894..c7a2a8d81d9009a0c14366a82cbd8ac83c370711 100644 (file)
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -93,46 +93,39 @@ struct drm_i915_mocs_table {
  *       may only be updated incrementally by adding entries at the
  *       end.
  */
+
+#define GEN9_MOCS_ENTRIES \
+       [I915_MOCS_UNCACHED] = { \
+               /* 0x00000009 */ \
+               .control_value = LE_1_UC | LE_TC_2_LLC_ELLC, \
+               /* 0x0010 */ \
+               .l3cc_value = L3_1_UC, \
+       }, \
+       [I915_MOCS_PTE] = { \
+               /* 0x00000038 */ \
+               .control_value = LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3), \
+               /* 0x0030 */ \
+               .l3cc_value = L3_3_WB, \
+       }
+
 static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
-       [I915_MOCS_UNCACHED] = {
-         /* 0x00000009 */
-         .control_value = LE_1_UC | LE_TC_2_LLC_ELLC,
-         /* 0x0010 */
-         .l3cc_value =    L3_1_UC,
-       },
-       [I915_MOCS_PTE] = {
-         /* 0x00000038 */
-         .control_value = LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3),
-         /* 0x0030 */
-         .l3cc_value =    L3_3_WB,
-       },
+       GEN9_MOCS_ENTRIES,
        [I915_MOCS_CACHED] = {
-         /* 0x0000003b */
-         .control_value = LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
-         /* 0x0030 */
-         .l3cc_value =   L3_3_WB,
+               /* 0x0000003b */
+               .control_value = LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
+               /* 0x0030 */
+               .l3cc_value =   L3_3_WB,
        },
 };
 
 /* NOTE: the LE_TGT_CACHE is not used on Broxton */
 static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
-       [I915_MOCS_UNCACHED] = {
-         /* 0x00000009 */
-         .control_value = LE_1_UC | LE_TC_2_LLC_ELLC,
-         /* 0x0010 */
-         .l3cc_value = L3_1_UC,
-       },
-       [I915_MOCS_PTE] = {
-         /* 0x00000038 */
-         .control_value = LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3),
-         /* 0x0030 */
-         .l3cc_value = L3_3_WB,
-       },
+       GEN9_MOCS_ENTRIES,
        [I915_MOCS_CACHED] = {
-         /* 0x00000039 */
-         .control_value = LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3),
-         /* 0x0030 */
-         .l3cc_value = L3_3_WB,
+               /* 0x00000039 */
+               .control_value = LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3),
+               /* 0x0030 */
+               .l3cc_value = L3_3_WB,
        },
 };