crypto: hisilicon/qm - print device abnormal information

When device is abnormal and reports abnormal interrupt event to driver,
the driver can print device information for error analysis. This patch
adds some device error-related information output after the device reports
an abnormal interrupt.

Signed-off-by: Weili Qian <qianweili@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c
index 18599f3634c3c1bc0adde2402cf8d12c119c0ae1..4d91a249be74d3d9bc3200d34baf92d15965fb40 100644 (file)
--- a/drivers/crypto/hisilicon/qm.c
+++ b/drivers/crypto/hisilicon/qm.c
@@ -129,16 +129,21 @@
 #define QM_FIFO_OVERFLOW_TYPE          0xc0
 #define QM_FIFO_OVERFLOW_TYPE_SHIFT    6
 #define QM_FIFO_OVERFLOW_VF            0x3f
+#define QM_FIFO_OVERFLOW_QP_SHIFT      16
 #define QM_ABNORMAL_INF01              0x100014
 #define QM_DB_TIMEOUT_TYPE             0xc0
 #define QM_DB_TIMEOUT_TYPE_SHIFT       6
 #define QM_DB_TIMEOUT_VF               0x3f
+#define QM_DB_TIMEOUT_QP_SHIFT         16
+#define QM_ABNORMAL_INF02              0x100018
+#define QM_AXI_POISON_ERR              BIT(22)
 #define QM_RAS_CE_ENABLE               0x1000ec
 #define QM_RAS_FE_ENABLE               0x1000f0
 #define QM_RAS_NFE_ENABLE              0x1000f4
 #define QM_RAS_CE_THRESHOLD            0x1000f8
 #define QM_RAS_CE_TIMES_PER_IRQ                1
 #define QM_OOO_SHUTDOWN_SEL            0x1040f8
+#define QM_AXI_RRESP_ERR               BIT(0)
 #define QM_ECC_MBIT                    BIT(2)
 #define QM_DB_TIMEOUT                  BIT(10)
 #define QM_OF_FIFO_OF                  BIT(11)
@@ -1406,7 +1411,7 @@ static void qm_log_hw_error(struct hisi_qm *qm, u32 error_status)
 {
        const struct hisi_qm_hw_error *err;
        struct device *dev = &qm->pdev->dev;
-       u32 reg_val, type, vf_num;
+       u32 reg_val, type, vf_num, qp_id;
        int i;
 
        for (i = 0; i < ARRAY_SIZE(qm_hw_error); i++) {
@@ -1422,19 +1427,24 @@ static void qm_log_hw_error(struct hisi_qm *qm, u32 error_status)
                        type = (reg_val & QM_DB_TIMEOUT_TYPE) >>
                               QM_DB_TIMEOUT_TYPE_SHIFT;
                        vf_num = reg_val & QM_DB_TIMEOUT_VF;
-                       dev_err(dev, "qm %s doorbell timeout in function %u\n",
-                               qm_db_timeout[type], vf_num);
+                       qp_id = reg_val >> QM_DB_TIMEOUT_QP_SHIFT;
+                       dev_err(dev, "qm %s doorbell timeout in function %u qp %u\n",
+                               qm_db_timeout[type], vf_num, qp_id);
                } else if (err->int_msk & QM_OF_FIFO_OF) {
                        reg_val = readl(qm->io_base + QM_ABNORMAL_INF00);
                        type = (reg_val & QM_FIFO_OVERFLOW_TYPE) >>
                               QM_FIFO_OVERFLOW_TYPE_SHIFT;
                        vf_num = reg_val & QM_FIFO_OVERFLOW_VF;
-
+                       qp_id = reg_val >> QM_FIFO_OVERFLOW_QP_SHIFT;
                        if (type < ARRAY_SIZE(qm_fifo_overflow))
-                               dev_err(dev, "qm %s fifo overflow in function %u\n",
-                                       qm_fifo_overflow[type], vf_num);
+                               dev_err(dev, "qm %s fifo overflow in function %u qp %u\n",
+                                       qm_fifo_overflow[type], vf_num, qp_id);
                        else
                                dev_err(dev, "unknown error type\n");
+               } else if (err->int_msk & QM_AXI_RRESP_ERR) {
+                       reg_val = readl(qm->io_base + QM_ABNORMAL_INF02);
+                       if (reg_val & QM_AXI_POISON_ERR)
+                               dev_err(dev, "qm axi poison error happened\n");
                }
        }
 }