]> www.infradead.org Git - users/hch/misc.git/commitdiff
ice: Refactor E825C PHY registers info struct
authorKarol Kolacinski <karol.kolacinski@intel.com>
Mon, 10 Mar 2025 17:44:56 +0000 (10:44 -0700)
committerPaolo Abeni <pabeni@redhat.com>
Tue, 18 Mar 2025 09:15:49 +0000 (10:15 +0100)
Simplify ice_phy_reg_info_eth56g struct definition to include base
address for the very first quad. Use base address info and 'step'
value to determine address for specific PHY quad.

Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Link: https://patch.msgid.link/20250310174502.3708121-4-anthony.l.nguyen@intel.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
drivers/net/ethernet/intel/ice/ice_ptp_consts.h
drivers/net/ethernet/intel/ice/ice_ptp_hw.c
drivers/net/ethernet/intel/ice/ice_ptp_hw.h

index ac46d1183300701589bc5f81f69ad44d84398798..003cdfada3ca820653e387fe9aec923018fc2427 100644 (file)
 /* Constants defined for the PTP 1588 clock hardware. */
 
 const struct ice_phy_reg_info_eth56g eth56g_phy_res[NUM_ETH56G_PHY_RES] = {
-       /* ETH56G_PHY_REG_PTP */
-       {
-               /* base_addr */
-               {
-                       0x092000,
-                       0x126000,
-                       0x1BA000,
-                       0x24E000,
-                       0x2E2000,
-               },
-               /* step */
-               0x98,
+       [ETH56G_PHY_REG_PTP] = {
+               .base_addr = 0x092000,
+               .step = 0x98,
        },
-       /* ETH56G_PHY_MEM_PTP */
-       {
-               /* base_addr */
-               {
-                       0x093000,
-                       0x127000,
-                       0x1BB000,
-                       0x24F000,
-                       0x2E3000,
-               },
-               /* step */
-               0x200,
+       [ETH56G_PHY_MEM_PTP] = {
+               .base_addr = 0x093000,
+               .step = 0x200,
        },
-       /* ETH56G_PHY_REG_XPCS */
-       {
-               /* base_addr */
-               {
-                       0x000000,
-                       0x009400,
-                       0x128000,
-                       0x1BC000,
-                       0x250000,
-               },
-               /* step */
-               0x21000,
+       [ETH56G_PHY_REG_XPCS] = {
+               .base_addr = 0x000000,
+               .step = 0x21000,
        },
-       /* ETH56G_PHY_REG_MAC */
-       {
-               /* base_addr */
-               {
-                       0x085000,
-                       0x119000,
-                       0x1AD000,
-                       0x241000,
-                       0x2D5000,
-               },
-               /* step */
-               0x1000,
+       [ETH56G_PHY_REG_MAC] = {
+               .base_addr = 0x085000,
+               .step = 0x1000,
        },
-       /* ETH56G_PHY_REG_GPCS */
-       {
-               /* base_addr */
-               {
-                       0x084000,
-                       0x118000,
-                       0x1AC000,
-                       0x240000,
-                       0x2D4000,
-               },
-               /* step */
-               0x400,
+       [ETH56G_PHY_REG_GPCS] = {
+               .base_addr = 0x084000,
+               .step = 0x400,
        },
 };
 
index fbaf2819e40e96d3e1b099ff35baefe270e79e50..89bb8461284ade1630fd54909109640519b18c6d 100644 (file)
@@ -1010,7 +1010,7 @@ static int ice_phy_res_address_eth56g(struct ice_hw *hw, u8 lane,
 
        /* Lanes 4..7 are in fact 0..3 on a second PHY */
        lane %= hw->ptp.ports_per_phy;
-       *addr = eth56g_phy_res[res_type].base[0] +
+       *addr = eth56g_phy_res[res_type].base_addr +
                lane * eth56g_phy_res[res_type].step + offset;
 
        return 0;
@@ -1240,7 +1240,7 @@ static int ice_write_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port,
        if (port >= hw->ptp.num_lports)
                return -EIO;
 
-       addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base[0] + offset;
+       addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset;
 
        return ice_write_phy_eth56g(hw, port, addr, val);
 }
@@ -1265,7 +1265,7 @@ static int ice_read_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port,
        if (port >= hw->ptp.num_lports)
                return -EIO;
 
-       addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base[0] + offset;
+       addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset;
 
        return ice_read_phy_eth56g(hw, port, addr, val);
 }
index 8442d1d603517aba08121a540ce862a0c8f58fbf..cca81391b6ad0439d8da4fd9dc5513326121111f 100644 (file)
@@ -65,14 +65,14 @@ enum ice_eth56g_link_spd {
 
 /**
  * struct ice_phy_reg_info_eth56g - ETH56G PHY register parameters
- * @base: base address for each PHY block
+ * @base_addr: base address for each PHY block
  * @step: step between PHY lanes
  *
  * Characteristic information for the various PHY register parameters in the
  * ETH56G devices
  */
 struct ice_phy_reg_info_eth56g {
-       u32 base[NUM_ETH56G_PHY_RES];
+       u32 base_addr;
        u32 step;
 };