ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
                                 val, !(val & GEN_CMD_FULL), 1000,
                                 CMD_PKT_STATUS_TIMEOUT_US);
-       if (ret < 0) {
+       if (ret) {
                dev_err(dsi->dev, "failed to get available command FIFO\n");
                return ret;
        }
        ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
                                 val, (val & mask) == mask,
                                 1000, CMD_PKT_STATUS_TIMEOUT_US);
-       if (ret < 0) {
+       if (ret) {
                dev_err(dsi->dev, "failed to write command FIFO\n");
                return ret;
        }
                ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
                                         val, !(val & GEN_PLD_W_FULL), 1000,
                                         CMD_PKT_STATUS_TIMEOUT_US);
-               if (ret < 0) {
+               if (ret) {
                        dev_err(dsi->dev,
                                "failed to get available write payload FIFO\n");
                        return ret;
 
        ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
                                 val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US);
-       if (ret < 0)
+       if (ret)
                DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
 
        ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
                                 val, val & PHY_STOP_STATE_CLK_LANE, 1000,
                                 PHY_STATUS_TIMEOUT_US);
-       if (ret < 0)
+       if (ret)
                DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
 }