drm/amd/display: Add odm seamless boot support

[WHY]
Implement changes to transition from Pre-OS odm to
Post-OS odm support. Seamless boot case is also
considered.

[HOW]
Revised validation logic when marking for seamless
boot. Init resources accordingly when Pre-OS has
odm enabled. Reset odm and det size when transitioning
Pre-OS odm to Post-OS non-odm to avoid corruption.
Apply logic to set odm accordingly upon commit.

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Duncan Ma <Duncan.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c436db416708e3f8f857e9cc5d8abbcc6f34d77d..c2fcd67bcc4d7a624986b7f30516fc7a0c0170c2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1569,11 +1569,24 @@ bool dc_validate_boot_timing(const struct dc *dc,
 
        if (dc_is_dp_signal(link->connector_signal)) {
                unsigned int pix_clk_100hz;
+               uint32_t numOdmPipes = 1;
+               uint32_t id_src[4] = {0};
 
                dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
                        dc->res_pool->dp_clock_source,
                        tg_inst, &pix_clk_100hz);
 
+               if (tg->funcs->get_optc_source)
+                       tg->funcs->get_optc_source(tg,
+                                               &numOdmPipes, &id_src[0], &id_src[1]);
+
+               if (numOdmPipes == 2)
+                       pix_clk_100hz *= 2;
+               if (numOdmPipes == 4)
+                       pix_clk_100hz *= 4;
+
+               // Note: In rare cases, HW pixclk may differ from crtc's pixclk
+               // slightly due to rounding issues in 10 kHz units.
                if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
                        return false;
 

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index f5777a71f2f1aef313bbc2ec357dba3b21d82efd..f292303b75a50b3643f4cc8f135a4df4c4f44d22 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2120,6 +2120,8 @@ static int acquire_resource_from_hw_enabled_state(
 {
        struct dc_link *link = stream->link;
        unsigned int i, inst, tg_inst = 0;
+       uint32_t numPipes = 1;
+       uint32_t id_src[4] = {0};
 
        /* Check for enabled DIG to identify enabled display */
        if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
@@ -2148,38 +2150,62 @@ static int acquire_resource_from_hw_enabled_state(
        if (!res_ctx->pipe_ctx[tg_inst].stream) {
                struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
 
-               pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
-               pipe_ctx->plane_res.mi = pool->mis[tg_inst];
-               pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
-               pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
-               pipe_ctx->plane_res.xfm = pool->transforms[tg_inst];
-               pipe_ctx->plane_res.dpp = pool->dpps[tg_inst];
-               pipe_ctx->stream_res.opp = pool->opps[tg_inst];
-
-               if (pool->dpps[tg_inst]) {
-                       pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
-
-                       // Read DPP->MPCC->OPP Pipe from HW State
-                       if (pool->mpc->funcs->read_mpcc_state) {
-                               struct mpcc_state s = {0};
-
-                               pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
-
-                               if (s.dpp_id < MAX_MPCC)
-                                       pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = s.dpp_id;
-
-                               if (s.bot_mpcc_id < MAX_MPCC)
-                                       pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
-                                                       &pool->mpc->mpcc_array[s.bot_mpcc_id];
+               id_src[0] = tg_inst;
+
+               if (pipe_ctx->stream_res.tg->funcs->get_optc_source)
+                       pipe_ctx->stream_res.tg->funcs->get_optc_source(pipe_ctx->stream_res.tg,
+                                       &numPipes, &id_src[0], &id_src[1]);
+
+               for (i = 0; i < numPipes; i++) {
+                       //Check if src id invalid
+                       if (id_src[i] == 0xf)
+                               return -1;
+
+                       pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
+                       pipe_ctx->plane_res.mi = pool->mis[id_src[i]];
+                       pipe_ctx->plane_res.hubp = pool->hubps[id_src[i]];
+                       pipe_ctx->plane_res.ipp = pool->ipps[id_src[i]];
+                       pipe_ctx->plane_res.xfm = pool->transforms[id_src[i]];
+                       pipe_ctx->plane_res.dpp = pool->dpps[id_src[i]];
+                       pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
+
+                       if (pool->dpps[id_src[i]]) {
+                               pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst;
+
+                               if (pool->mpc->funcs->read_mpcc_state) {
+                                       struct mpcc_state s = {0};
+                                       pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
+                                       if (s.dpp_id < MAX_MPCC)
+                                               pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id =
+                                                               s.dpp_id;
+                                       if (s.bot_mpcc_id < MAX_MPCC)
+                                               pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
+                                                               &pool->mpc->mpcc_array[s.bot_mpcc_id];
+                                       if (s.opp_id < MAX_OPP)
+                                               pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
+                               }
+                       }
+                       pipe_ctx->pipe_idx = id_src[i];
 
-                               if (s.opp_id < MAX_OPP)
-                                       pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
+                       if (id_src[i] >= pool->timing_generator_count) {
+                               id_src[i] = pool->timing_generator_count - 1;
+                               pipe_ctx->stream_res.tg = pool->timing_generators[id_src[i]];
+                               pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
                        }
+
+                       pipe_ctx->stream = stream;
                }
-               pipe_ctx->pipe_idx = tg_inst;
 
-               pipe_ctx->stream = stream;
-               return tg_inst;
+               if (numPipes == 2) {
+                       stream->apply_boot_odm_mode = dm_odm_combine_policy_2to1;
+                       res_ctx->pipe_ctx[id_src[0]].next_odm_pipe = &res_ctx->pipe_ctx[id_src[1]];
+                       res_ctx->pipe_ctx[id_src[0]].prev_odm_pipe = NULL;
+                       res_ctx->pipe_ctx[id_src[1]].next_odm_pipe = NULL;
+                       res_ctx->pipe_ctx[id_src[1]].prev_odm_pipe = &res_ctx->pipe_ctx[id_src[0]];
+               } else
+                       stream->apply_boot_odm_mode = dm_odm_combine_mode_disabled;
+
+               return id_src[0];
        }
 
        return -1;

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index e723553f9c5ac6a5d52e73674c956930af4136ef..863d90bec61b29ba6020e586a15c299a8ff0a7fb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -666,6 +666,7 @@ struct dc_debug_options {
        uint32_t edid_read_retry_times;
        bool remove_disconnect_edp;
        unsigned int force_odm_combine; //bit vector based on otg inst
+       unsigned int seamless_boot_odm_combine;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
        unsigned int force_odm_combine_4to1; //bit vector based on otg inst
        bool disable_z9_mpc;

diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index c4168c11257c310778ef1e08e00635bed6aabffc..580420c3eedc4521343dc76f31623dee84ceb6d4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -246,6 +246,7 @@ struct dc_stream_state {
 
        bool apply_edp_fast_boot_optimization;
        bool apply_seamless_boot_optimization;
+       uint32_t apply_boot_odm_mode;
 
        uint32_t stream_id;
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 6c69fd3bc77a959f20e0fe67600c17f0233ec13b..e02ac75afbf756e66fc9e01889b1aa4827502ee0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1259,6 +1259,7 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
 {
        int i;
        struct dce_hwseq *hws = dc->hwseq;
+       struct hubbub *hubbub = dc->res_pool->hubbub;
        bool can_apply_seamless_boot = false;
 
        for (i = 0; i < context->stream_count; i++) {
@@ -1294,6 +1295,21 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
                }
        }
 
+       /* Reset det size */
+       for (i = 0; i < dc->res_pool->pipe_count; i++) {
+               struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+               struct hubp *hubp = dc->res_pool->hubps[i];
+
+               /* Do not need to reset for seamless boot */
+               if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
+                       continue;
+
+               if (hubbub && hubp) {
+                       if (hubbub->funcs->program_det_size)
+                               hubbub->funcs->program_det_size(hubbub, hubp->inst, 0);
+               }
+       }
+
        /* num_opp will be equal to number of mpcc */
        for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
                struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
@@ -1359,6 +1375,11 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
                pipe_ctx->stream_res.tg = NULL;
                pipe_ctx->plane_res.hubp = NULL;
 
+               if (tg->funcs->is_tg_enabled(tg)) {
+                       if (tg->funcs->init_odm)
+                               tg->funcs->init_odm(tg);
+               }
+
                tg->funcs->tg_init(tg);
        }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
index 10f897b1cb63cabbca6b588f0397c3b656514362..c51f7dca94f8e8b225baf5d2a7472085e7e24950 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
@@ -213,6 +213,26 @@ void optc31_set_drr(
        }
 }
 
+void optc3_init_odm(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
+                       OPTC_NUM_OF_INPUT_SEGMENT, 0,
+                       OPTC_SEG0_SRC_SEL, optc->inst,
+                       OPTC_SEG1_SRC_SEL, 0xf,
+                       OPTC_SEG2_SRC_SEL, 0xf,
+                       OPTC_SEG3_SRC_SEL, 0xf
+                       );
+
+       REG_SET(OTG_H_TIMING_CNTL, 0,
+                       OTG_H_TIMING_DIV_MODE, 0);
+
+       REG_SET(OPTC_MEMORY_CONFIG, 0,
+                       OPTC_MEM_SEL, 0);
+       optc1->opp_count = 1;
+}
+
 static struct timing_generator_funcs dcn31_tg_funcs = {
                .validate_timing = optc1_validate_timing,
                .program_timing = optc1_program_timing,
@@ -272,6 +292,7 @@ static struct timing_generator_funcs dcn31_tg_funcs = {
                .program_manual_trigger = optc2_program_manual_trigger,
                .setup_manual_trigger = optc2_setup_manual_trigger,
                .get_hw_timing = optc1_get_hw_timing,
+               .init_odm = optc3_init_odm,
 };
 
 void dcn31_timing_generator_init(struct optc *optc1)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
index a37b16040c1d6bae78b271bcc20b4d3367449341..9e881f2ce74baccf48ff045d54c62c0c5194d283 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
@@ -258,4 +258,6 @@ void dcn31_timing_generator_init(struct optc *optc1);
 
 void optc31_set_drr(struct timing_generator *optc, const struct drr_params *params);
 
+void optc3_init_odm(struct timing_generator *optc);
+
 #endif /* __DC_OPTC_DCN31_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 59a704781e3490af8dd86f2b9e0f234337a7faf8..554d2e33bd7f1bb4c6df7b4e3d82e69266d4c3a2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -310,6 +310,8 @@ struct timing_generator_funcs {
                        uint32_t slave_pixel_clock_100Hz,
                        uint8_t master_clock_divider,
                        uint8_t slave_clock_divider);
+
+       void (*init_odm)(struct timing_generator *tg);
 };
 
 #endif