Blackfin: bf51x: fix alternative portmux options

The BF51x's alternative portmux Kconfig options were copy & pasted from
the BF52x, but never tweaked to reflect it.  So drop the old options as
they were never used (and were simply wrong), and add the BF51x specific
pieces to the Kconfig and header.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

diff --git a/arch/blackfin/mach-bf518/Kconfig b/arch/blackfin/mach-bf518/Kconfig
index 1d9f631a7f949a915dad8e87ebb7c927ec793a8c..bde92a19970e11fe80243c61f1cf7e0b42711cb8 100644 (file)
--- a/arch/blackfin/mach-bf518/Kconfig
+++ b/arch/blackfin/mach-bf518/Kconfig
@@ -11,55 +11,75 @@ menu "BF518 Specific Configuration"
 comment "Alternative Multiplexing Scheme"
 
 choice
-       prompt "SPORT0"
-       default BF518_SPORT0_PORTG
+       prompt "PWM Channel Pins"
+       default BF518_PWM_ALL_PORTF
        help
-         Select PORT used for SPORT0. See Hardware Reference Manual
+         Select pins used for the PWM channels:
+           PWM_AH PWM_AL PWM_BH PWM_BL PWM_CH PWM_CL
 
-config BF518_SPORT0_PORTF
-       bool "PORT F"
+         See the Hardware Reference Manual for more details.
+
+config BF518_PWM_ALL_PORTF
+       bool "PF1 - PF6"
        help
-         PORT F
+         PF{1,2,3,4,5,6} <-> PWM_{AH,AL,BH,BL,CH,CL}
 
-config BF518_SPORT0_PORTG
-       bool "PORT G"
+config BF518_PWM_PORTF_PORTG
+       bool "PF11 - PF14 / PG1 - PG2"
        help
-         PORT G
+         PF{11,12,13,14} <-> PWM_{AH,AL,BH,BL}
+         PG{1,2} <-> PWM_{CH,CL}
+
 endchoice
 
 choice
-       prompt "SPORT0 TSCLK Location"
-       depends on BF518_SPORT0_PORTG
-       default BF518_SPORT0_TSCLK_PG10
+       prompt "PWM Sync Pin"
+       default BF518_PWM_SYNC_PF7
        help
-         Select PIN used for SPORT0_TSCLK. See Hardware Reference Manual
+         Select the pin used for PWM_SYNC.
 
-config BF518_SPORT0_TSCLK_PG10
-       bool "PORT PG10"
-       help
-         PORT PG10
+         See the Hardware Reference Manual for more details.
+
+config BF518_PWM_SYNC_PF7
+       bool "PF7"
+config BF518_PWM_SYNC_PF15
+       bool "PF15"
+endchoice
 
-config BF518_SPORT0_TSCLK_PG14
-       bool "PORT PG14"
+choice
+       prompt "PWM Trip B Pin"
+       default BF518_PWM_TRIPB_PG10
        help
-         PORT PG14
+         Select the pin used for PWM_TRIPB.
+
+         See the Hardware Reference Manual for more details.
+
+config BF518_PWM_TRIPB_PG10
+       bool "PG10"
+config BF518_PWM_TRIPB_PG14
+       bool "PG14"
 endchoice
 
 choice
-       prompt "UART1"
-       default BF518_UART1_PORTF
+       prompt "PPI / Timer Pins"
+       default BF518_PPI_TMR_PG5
        help
-         Select PORT used for UART1. See Hardware Reference Manual
+         Select pins used for PPI/Timer:
+           PPICLK PPIFS1 PPIFS2
+           TMRCLK TMR0 TMR1
 
-config BF518_UART1_PORTF
-       bool "PORT F"
+         See the Hardware Reference Manual for more details.
+
+config BF518_PPI_TMR_PG5
+       bool "PG5 - PG7"
        help
-         PORT F
+         PG{5,6,7} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2}
 
-config BF518_UART1_PORTG
-       bool "PORT G"
+config BF518_PPI_TMR_PG12
+       bool "PG12 - PG14"
        help
-         PORT G
+         PG{12,13,14} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2}
+
 endchoice
 
 comment "Hysteresis/Schmitt Trigger Control"

diff --git a/arch/blackfin/mach-bf518/include/mach/portmux.h b/arch/blackfin/mach-bf518/include/mach/portmux.h
index cd84a569b04eed5189a0f69dbdaf894ad0e733b4..b3b806f468daead345e31899b9422e12287dbc5c 100644 (file)
--- a/arch/blackfin/mach-bf518/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf518/include/mach/portmux.h
@@ -81,9 +81,15 @@
 #define P_PPI0_D14     (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
 #define P_PPI0_D15     (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
 
+#ifndef CONFIG_BF518_PPI_TMR_PG12
+#define P_PPI0_CLK     (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
+#define P_PPI0_FS1     (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
+#define P_PPI0_FS2     (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
+#else
 #define P_PPI0_CLK     (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
 #define P_PPI0_FS1     (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
 #define P_PPI0_FS2     (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
+#endif
 #define P_PPI0_FS3     (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
 
 /* SPI Port Mux */
@@ -139,9 +145,15 @@
 #define P_UART1_RX     (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
 
 /* Timer */
+#ifndef CONFIG_BF518_PPI_TMR_PG12
 #define P_TMRCLK       (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
 #define P_TMR0         (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
 #define P_TMR1         (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
+#else
+#define P_TMRCLK       (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
+#define P_TMR0         (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
+#define P_TMR1         (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
+#endif
 #define P_TMR2         (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
 #define P_TMR3         (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
 #define P_TMR4         (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
@@ -158,23 +170,33 @@
 #define P_TWI0_SDA     (P_DONTCARE)
 
 /* PWM */
-#define P_PWM0_AH              (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_PWM0_AL              (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_PWM0_BH              (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_PWM0_BL              (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_PWM0_CH              (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_PWM0_CL              (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_PWM0_SYNC            (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-
-#define P_PWM1_AH              (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
-#define P_PWM1_AL              (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_PWM1_BH              (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-#define P_PWM1_BL              (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_PWM1_CH              (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_PWM1_CL              (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_PWM1_SYNC            (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-
+#ifndef CONFIG_BF518_PWM_PORTF_PORTG
+#define P_PWM_AH               (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
+#define P_PWM_AL               (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
+#define P_PWM_BH               (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
+#define P_PWM_BL               (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
+#define P_PWM_CH               (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
+#define P_PWM_CL               (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
+#else
+#define P_PWM_AH               (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
+#define P_PWM_AL               (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
+#define P_PWM_BH               (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
+#define P_PWM_BL               (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
+#define P_PWM_CH               (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
+#define P_PWM_CL               (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
+#endif
+
+#ifndef CONFIG_BF518_PWM_SYNC_PF15
+#define P_PWM_SYNC             (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
+#else
+#define P_PWM_SYNC             (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
+#endif
+
+#ifndef CONFIG_BF518_PWM_TRIPB_PG14
+#define P_PWM_TRIPB            (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2))
+#else
 #define P_PWM_TRIPB            (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
+#endif
 
 /* RSI */
 #define P_RSI_DATA0            (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))