PCI: mediatek: Assert PERST# for 100ms for power and clock to stabilize

Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
be delayed 100ms (TPVPERL) for the power and clock to become stable.

Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com
Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Pali Rohár <pali@kernel.org>

diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index 2f3f974977a362accbd04a72a8ea177ab1d9f6ac..b18935e8da89a4425944dee142366142ddc0eca5 100644 (file)
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
         */
        writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
 
+       /*
+        * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
+        * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
+        * be delayed 100ms (TPVPERL) for the power and clock to become stable.
+        */
+       msleep(100);
+
        /* De-assert PHY, PE, PIPE, MAC and configuration reset */
        val = readl(port->base + PCIE_RST_CTRL);
        val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |