#define VERSION                      (0xF << 25)
 #define CIVERSION            (0x7 << 29)
 
+/* SBUSCFG */
+#define AHBBRST_MASK           0x7
+
 /* HCCPARAMS */
 #define HCCPARAMS_LEN         BIT(17)
 
 
 
        hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
 
+       if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
+               hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
+                       ci->platdata->ahb_burst_config);
 }
 
 /**
                }
        }
 
+       if (of_find_property(dev->of_node, "ahb-burst-config", NULL)) {
+               ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
+                       &platdata->ahb_burst_config);
+               if (ret) {
+                       dev_err(dev,
+                               "failed to get ahb-burst-config\n");
+                       return ret;
+               }
+               platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
+       }
+
        return 0;
 }
 
 
 #define CI_HDRC_FORCE_FULLSPEED                BIT(6)
 #define CI_HDRC_TURN_VBUS_EARLY_ON     BIT(7)
 #define CI_HDRC_SET_NON_ZERO_TTHA      BIT(8)
+#define CI_HDRC_OVERRIDE_AHB_BURST     BIT(9)
        enum usb_dr_mode        dr_mode;
 #define CI_HDRC_CONTROLLER_RESET_EVENT         0
 #define CI_HDRC_CONTROLLER_STOPPED_EVENT       1
        bool                    tpl_support;
        /* interrupt threshold setting */
        u32                     itc_setting;
+       u32                     ahb_burst_config;
 };
 
 /* Default offset of capability registers */