drm/amd/display: Determine IPS mode by ASIC and PMFW versions

[Why]

DCN IPS interoperates with other system idle power features, such as
Zstates.

On DCN35, there is a known issue where system Z8 + DCN IPS2 causes a
hard hang. We observe this on systems where the SBIOS allows Z8.

Though there is a SBIOS fix, there's no guarantee that users will get it
any time soon, or even install it. A workaround is needed to prevent
this from rearing its head in the wild.

[How]

For DCN35, check the pmfw version to determine whether the SBIOS has the
fix. If not, set IPS1+RCG as the deepest possible state in all cases
except for s0ix and display off (DPMS). Otherwise, enable all IPS

Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 28d43d0895896f84c038d906d244e0a95eb243ec)
Cc: stable@vger.kernel.org

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 983a977632ff4e263b588dc5d140315f3e8e65fe..e6cea5b9bdb35d215a44ea22eae55484ed831709 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1752,6 +1752,30 @@ static struct dml2_soc_bb *dm_dmub_get_vbios_bounding_box(struct amdgpu_device *
        return bb;
 }
 
+static enum dmub_ips_disable_type dm_get_default_ips_mode(
+       struct amdgpu_device *adev)
+{
+       /*
+        * On DCN35 systems with Z8 enabled, it's possible for IPS2 + Z8 to
+        * cause a hard hang. A fix exists for newer PMFW.
+        *
+        * As a workaround, for non-fixed PMFW, force IPS1+RCG as the deepest
+        * IPS state in all cases, except for s0ix and all displays off (DPMS),
+        * where IPS2 is allowed.
+        *
+        * When checking pmfw version, use the major and minor only.
+        */
+       if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(3, 5, 0) &&
+           (adev->pm.fw_version & 0x00FFFF00) < 0x005D6300)
+               return DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
+
+       if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 5, 0))
+               return DMUB_IPS_ENABLE;
+
+       /* ASICs older than DCN35 do not have IPSs */
+       return DMUB_IPS_DISABLE_ALL;
+}
+
 static int amdgpu_dm_init(struct amdgpu_device *adev)
 {
        struct dc_init_data init_data;
@@ -1863,7 +1887,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
        if (amdgpu_dc_debug_mask & DC_DISABLE_IPS)
                init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL;
        else
-               init_data.flags.disable_ips = DMUB_IPS_ENABLE;
+               init_data.flags.disable_ips = dm_get_default_ips_mode(adev);
 
        init_data.flags.disable_ips_in_vpb = 0;