drm/i915/psr: Program default IO buffer Wake and Fast Wake

The IO buffer Wake and Fast Wake bit size and value have been changed from
Gen12+. It programs the default value of IO buffer Wake and Fast Wake on
Gen12+. It adds definitions of IO buffer Wake and Fast Wake for pre Gen12
and Gen12+. And it aligns PSR2 definition macros.

v2: Fix macro definitions. (José)
v3: Addressed review comments from José
  - Add missing default values of IO_BUFFER_WAKE and FAST_WAKE for GEN9+
  - Change a style of macro naming in order to use lines as input.
  - Update Todo comments.
v4: Add parentheses to macros to avoid precedence issues.

Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200607143614.185246-1-gwan-gyeong.mun@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 7a0011e42e0021df144f3befa41e18f5f489cdf0..ab380e6dc674dad8e41e16575a2c7a66212a52e7 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -537,6 +537,22 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
        val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
        val |= intel_psr2_get_tp_time(intel_dp);
 
+       if (INTEL_GEN(dev_priv) >= 12) {
+               /*
+                * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default
+                * values from BSpec. In order to setting an optimal power
+                * consumption, lower than 4k resoluition mode needs to decrese
+                * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution
+                * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE.
+                */
+               val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
+               val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7);
+               val |= TGL_EDP_PSR2_FAST_WAKE(7);
+       } else if (INTEL_GEN(dev_priv) >= 9) {
+               val |= EDP_PSR2_IO_BUFFER_WAKE(7);
+               val |= EDP_PSR2_FAST_WAKE(7);
+       }
+
        /*
         * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
         * recommending keep this bit unset while PSR2 is enabled.

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 814a709454687a84b118394588fa338a934859ed..4066f67175dc19500d3bc64cd5cef10776811cb8 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4511,25 +4511,39 @@ enum {
 #define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1 << 16) /* Reserved in ICL+ */
 #define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
 
-#define _PSR2_CTL_A                    0x60900
-#define _PSR2_CTL_EDP                  0x6f900
-#define EDP_PSR2_CTL(tran)             _MMIO_TRANS2(tran, _PSR2_CTL_A)
-#define   EDP_PSR2_ENABLE              (1 << 31)
-#define   EDP_SU_TRACK_ENABLE          (1 << 30)
-#define   EDP_Y_COORDINATE_VALID       (1 << 26) /* GLK and CNL+ */
-#define   EDP_Y_COORDINATE_ENABLE      (1 << 25) /* GLK and CNL+ */
-#define   EDP_MAX_SU_DISABLE_TIME(t)   ((t) << 20)
-#define   EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20)
-#define   EDP_PSR2_TP2_TIME_500us      (0 << 8)
-#define   EDP_PSR2_TP2_TIME_100us      (1 << 8)
-#define   EDP_PSR2_TP2_TIME_2500us     (2 << 8)
-#define   EDP_PSR2_TP2_TIME_50us       (3 << 8)
-#define   EDP_PSR2_TP2_TIME_MASK       (3 << 8)
-#define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
-#define   EDP_PSR2_FRAME_BEFORE_SU_MASK        (0xf << 4)
-#define   EDP_PSR2_FRAME_BEFORE_SU(a)  ((a) << 4)
-#define   EDP_PSR2_IDLE_FRAME_MASK     0xf
-#define   EDP_PSR2_IDLE_FRAME_SHIFT    0
+#define _PSR2_CTL_A                            0x60900
+#define _PSR2_CTL_EDP                          0x6f900
+#define EDP_PSR2_CTL(tran)                     _MMIO_TRANS2(tran, _PSR2_CTL_A)
+#define   EDP_PSR2_ENABLE                      (1 << 31)
+#define   EDP_SU_TRACK_ENABLE                  (1 << 30)
+#define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_2       (0 << 28)
+#define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_3       (1 << 28)
+#define   EDP_Y_COORDINATE_VALID               (1 << 26) /* GLK and CNL+ */
+#define   EDP_Y_COORDINATE_ENABLE              (1 << 25) /* GLK and CNL+ */
+#define   EDP_MAX_SU_DISABLE_TIME(t)           ((t) << 20)
+#define   EDP_MAX_SU_DISABLE_TIME_MASK         (0x1f << 20)
+#define   EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES    8
+#define   EDP_PSR2_IO_BUFFER_WAKE(lines)       ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13)
+#define   EDP_PSR2_IO_BUFFER_WAKE_MASK         (3 << 13)
+#define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES        5
+#define   TGL_EDP_PSR2_IO_BUFFER_WAKE(lines)   (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13)
+#define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK     (7 << 13)
+#define   EDP_PSR2_FAST_WAKE_MAX_LINES         8
+#define   EDP_PSR2_FAST_WAKE(lines)            ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11)
+#define   EDP_PSR2_FAST_WAKE_MASK              (3 << 11)
+#define   TGL_EDP_PSR2_FAST_WAKE_MIN_LINES     5
+#define   TGL_EDP_PSR2_FAST_WAKE(lines)                (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10)
+#define   TGL_EDP_PSR2_FAST_WAKE_MASK          (7 << 10)
+#define   EDP_PSR2_TP2_TIME_500us              (0 << 8)
+#define   EDP_PSR2_TP2_TIME_100us              (1 << 8)
+#define   EDP_PSR2_TP2_TIME_2500us             (2 << 8)
+#define   EDP_PSR2_TP2_TIME_50us               (3 << 8)
+#define   EDP_PSR2_TP2_TIME_MASK               (3 << 8)
+#define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT       4
+#define   EDP_PSR2_FRAME_BEFORE_SU_MASK                (0xf << 4)
+#define   EDP_PSR2_FRAME_BEFORE_SU(a)          ((a) << 4)
+#define   EDP_PSR2_IDLE_FRAME_MASK             0xf
+#define   EDP_PSR2_IDLE_FRAME_SHIFT            0
 
 #define _PSR_EVENT_TRANS_A                     0x60848
 #define _PSR_EVENT_TRANS_B                     0x61848