#define SPU_BASE 0x40000000
-#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */
-#define spu_LineStat_w 0x04 /* Line Status Register (Set) */
-#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */
-#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */
-#define spu_BRateDivh 0x10 /* Baud rate divisor high */
-#define spu_BRateDivl 0x14 /* Baud rate divisor low */
-#define spu_CtlReg 0x18 /* Control Register */
-#define spu_RxCmd 0x1c /* Rx Command Register */
-#define spu_TxCmd 0x20 /* Tx Command Register */
-#define spu_RxBuff 0x24 /* Rx data buffer */
-#define spu_TxBuff 0x24 /* Tx data buffer */
+#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */
+#define spu_LineStat_w 0x04 /* Line Status Register (Set) */
+#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */
+#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */
+#define spu_BRateDivh 0x10 /* Baud rate divisor high */
+#define spu_BRateDivl 0x14 /* Baud rate divisor low */
+#define spu_CtlReg 0x18 /* Control Register */
+#define spu_RxCmd 0x1c /* Rx Command Register */
+#define spu_TxCmd 0x20 /* Tx Command Register */
+#define spu_RxBuff 0x24 /* Rx data buffer */
+#define spu_TxBuff 0x24 /* Tx data buffer */
/*-----------------------------------------------------------------------------+
| Line Status Register.
* as serial console interface.
*/
-void
-serial_init(ulong cpu_clock, int baudrate)
+void serial_init (ulong cpu_clock, int baudrate)
{
- volatile char val;
- unsigned short br_reg;
-
- br_reg = ((((CONFIG_CPUCLOCK * 1000000)/16) / baudrate)-1);
-
- /*
- * Init onboard UART
- */
- out8(SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
- out8(SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
- out8(SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
- out8(SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */
- out8(SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
- out8(SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
- out8(SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
- val = in8(SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
+ volatile char val;
+ unsigned short br_reg;
+
+ br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / baudrate) - 1);
+
+ /*
+ * Init onboard UART
+ */
+ out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
+ out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
+ out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
+ out8 (SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */
+ out8 (SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
+ out8 (SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
+ out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
+ val = in8 (SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
}
-void
-serial_setbrg (ulong cpu_clock, int baudrate)
+void serial_setbrg (ulong cpu_clock, int baudrate)
{
- unsigned short br_reg;
+ unsigned short br_reg;
- br_reg = ((((CONFIG_CPUCLOCK * 1000000)/16) / baudrate)-1);
+ br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / baudrate) - 1);
- out8(SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
- out8(SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
+ out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
+ out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
}
-void
-serial_putc(const char c)
+void serial_putc (const char c)
{
- if (c == '\n')
- serial_putc ('\r');
+ if (c == '\n')
+ serial_putc ('\r');
- /* load status from handshake register */
- if (in8(SPU_BASE + spu_Handshk_rc) != 00)
- out8(SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
+ /* load status from handshake register */
+ if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
+ out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
- out8(SPU_BASE + spu_TxBuff, c); /* Put char */
+ out8 (SPU_BASE + spu_TxBuff, c); /* Put char */
- while ((in8(SPU_BASE + spu_LineStat_rc) & 04) != 04)
- {
- if (in8(SPU_BASE + spu_Handshk_rc) != 00)
- out8(SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
- }
+ while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) {
+ if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
+ out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
+ }
}
-void
-serial_puts (const char *s)
+void serial_puts (const char *s)
{
- while (*s)
- {
- serial_putc (*s++);
- }
+ while (*s) {
+ serial_putc (*s++);
+ }
}
-int serial_getc()
+int serial_getc ()
{
- unsigned char status = 0;
-
- while(1)
- {
- status=in8(asyncLSRport1);
- if ((status&asyncLSRDataReady)!=0x0)
- {
- break;
- }
- else if ((status&(asyncLSRFramingError|asyncLSROverrunError|
- asyncLSRParityError|asyncLSRBreakInterrupt))!=0)
- {
- (void)out8(asyncLSRport1, asyncLSRFramingError|asyncLSROverrunError|
- asyncLSRParityError|asyncLSRBreakInterrupt);
- }
- }
- return(0x000000ff&(int)in8(asyncRxBufferport1));
+ unsigned char status = 0;
+
+ while (1) {
+ status = in8 (asyncLSRport1);
+ if ((status & asyncLSRDataReady) != 0x0) {
+ break;
+ }
+ if ((status & ( asyncLSRFramingError |
+ asyncLSROverrunError |
+ asyncLSRParityError |
+ asyncLSRBreakInterrupt )) != 0) {
+ (void) out8 (asyncLSRport1,
+ asyncLSRFramingError |
+ asyncLSROverrunError |
+ asyncLSRParityError |
+ asyncLSRBreakInterrupt );
+ }
+ }
+ return (0x000000ff & (int) in8 (asyncRxBufferport1));
}
-int
-serial_tstc()
+int serial_tstc ()
{
- unsigned char status;
-
- status=in8(asyncLSRport1);
- if ((status&asyncLSRDataReady)!=0x0)
- {
- return(1);
- }
- if ((status&(asyncLSRFramingError|asyncLSROverrunError|asyncLSRParityError|
- asyncLSRBreakInterrupt))!=0)
- {
- (void)out8(asyncLSRport1, asyncLSRFramingError|asyncLSROverrunError|
- asyncLSRParityError|asyncLSRBreakInterrupt);
- }
- return 0;
+ unsigned char status;
+
+ status = in8 (asyncLSRport1);
+ if ((status & asyncLSRDataReady) != 0x0) {
+ return (1);
+ }
+ if ((status & ( asyncLSRFramingError |
+ asyncLSROverrunError |
+ asyncLSRParityError |
+ asyncLSRBreakInterrupt )) != 0) {
+ (void) out8 (asyncLSRport1,
+ asyncLSRFramingError |
+ asyncLSROverrunError |
+ asyncLSRParityError |
+ asyncLSRBreakInterrupt);
+ }
+ return 0;
}
-#endif /* CONFIG_IOP480 */
+#endif /* CONFIG_IOP480 */
/*****************************************************************************/
#if defined(CONFIG_405GP) || defined(CONFIG_405CR)
-#define UART_BASE_PTR 0xF800FFFC; /* pointer to uart base */
+#define UART_BASE_PTR 0xF800FFFC; /* pointer to uart base */
#define UART0_BASE 0xef600300
#define UART1_BASE 0xef600400
| Fifo
+-----------------------------------------------------------------------------*/
typedef struct {
- char * rx_buffer;
- ulong rx_put;
- ulong rx_get;
+ char *rx_buffer;
+ ulong rx_put;
+ ulong rx_get;
} serial_buffer_t;
volatile static serial_buffer_t buf_info;
* as serial console interface.
*/
-void
-serial_init(ulong cpu_clock, int baudrate)
+void serial_init (ulong cpu_clock, int baudrate)
{
- volatile char val;
- unsigned short br_reg;
- unsigned long cntrl0Reg;
-
+ unsigned long reg;
+ unsigned long tmp;
+ unsigned long clk;
+ unsigned long udiv;
+ unsigned short bdiv;
+ volatile char val;
+
+ reg = mfdcr (cntrl0) & ~0x1fffUL;
#ifdef CFG_EXT_SERIAL_CLOCK
- /*
- * Use external clock to generate serial clock
- */
- cntrl0Reg = mfdcr(cntrl0) & 0xffffe000;
- cntrl0Reg |= 0x000010c0;
- mtdcr(cntrl0, cntrl0Reg);
- br_reg = (((CFG_EXT_SERIAL_CLOCK*10)/16) / baudrate + 5) / 10;
+ clk = CFG_EXT_SERIAL_CLOCK;
+ udiv = 1;
+ reg |= 0x10c0;
#else
- /*
- * Use internal cpu clock to generate serial clock
- */
-#ifdef CFG_IGNORE_405_UART_ERRATA_59
- /*
- * The divisor bits are STUCK on ALL IBM 405GP/CR Rev. D silicon.
- * RTF Errata!
- */
- cntrl0Reg = mfdcr(cntrl0) & 0xffffe000;
- cntrl0Reg |= 0x00001022;
- mtdcr(cntrl0, cntrl0Reg); /* serial clock = cpu clock / 18 */
- br_reg = (((((cpu_clock/16)/18) * 10) / baudrate) + 5) / 10 ;
+ clk = cpu_clock;
+#ifdef CFG_405_UART_ERRATA_59
+ udiv = 31; /* Errata 59: stuck at 31 */
#else
- cntrl0Reg = mfdcr(cntrl0) & 0xffffe000;
- cntrl0Reg |= 0x0000103c;
- mtdcr(cntrl0, cntrl0Reg); /* Divisor stuck at 31 */
- br_reg = ( ( (cpu_clock / (16 * (((mfdcr(cntrl0) & 0x3e) >> 1) + 1)) * 10)
- / baudrate ) + 5 ) / 10;
-#endif /* CFG_IGNORE_405_UART_ERRATA_59 */
-
-#endif /* CFG_EXT_SERIAL_CLOCK */
-
- /*
- * Init onboard 16550 UART
- */
- out8(UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
- out8(UART0_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
- out8(UART0_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
- out8(UART0_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
- out8(UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
- out8(UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
- val = in8(UART0_BASE + UART_LSR); /* clear line status */
- val = in8(UART0_BASE + UART_RBR); /* read receive buffer */
- out8(UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
- out8(UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
+ tmp = CFG_BASE_BAUD * 16;
+ udiv = (clk + tmp / 2) / tmp;
+#endif
+#endif
+ reg |= (udiv - 1) << 1; /* set the UART divisor */
+ mtdcr (cntrl0, reg);
+
+ tmp = baudrate * udiv * 16;
+ bdiv = (clk + tmp / 2) / tmp;
+
+ out8 (UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
+ out8 (UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
+ out8 (UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
+ out8 (UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
+ out8 (UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
+ out8 (UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
+ val = in8 (UART0_BASE + UART_LSR); /* clear line status */
+ val = in8 (UART0_BASE + UART_RBR); /* read receive buffer */
+ out8 (UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
+ out8 (UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
}
-void
-serial_setbrg (ulong cpu_clock, int baudrate)
+void serial_setbrg (ulong cpu_clock, int baudrate)
{
- unsigned short br_reg;
+ unsigned long tmp;
+ unsigned long clk;
+ unsigned long udiv;
+ unsigned short bdiv;
#ifdef CFG_EXT_SERIAL_CLOCK
- br_reg = (((CFG_EXT_SERIAL_CLOCK*10)/16) / baudrate + 5) / 10;
+ clk = CFG_EXT_SERIAL_CLOCK;
#else
-
-#ifdef CFG_IGNORE_405_UART_ERRATA_59
- /*
- * The divisor bits are STUCK on ALL IBM 405GP/CR Rev. D silicon.
- * RTF Errata!
- */
- br_reg = (((((cpu_clock/16)/18) * 10) / baudrate) + 5) / 10 ;
-#else
- br_reg = ( ( (cpu_clock / (16 * (((mfdcr(cntrl0) & 0x3e) >> 1) + 1)) * 10)
- / baudrate ) + 5 ) / 10;
-#endif /* CFG_IGNORE_405_UART_ERRATA_59 */
-
+ clk = cpu_clock;
#endif
-
- out8(UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
- out8(UART0_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
- out8(UART0_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
- out8(UART0_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
+ udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
+ tmp = baudrate * udiv * 16;
+ bdiv = (clk + tmp / 2) / tmp;
+
+ out8 (UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
+ out8 (UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
+ out8 (UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
+ out8 (UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
}
-void
-serial_putc(const char c)
+void serial_putc (const char c)
{
- int i;
- if (c == '\n')
- serial_putc ('\r');
-
- /* check THRE bit, wait for transmiter available */
- for(i = 1; i < 3500 ; i++) {
- if ((in8(UART0_BASE + UART_LSR) & 0x20) == 0x20)
- break;
- udelay(100);
- }
- out8(UART0_BASE + UART_THR, c); /* put character out */
+ int i;
+
+ if (c == '\n')
+ serial_putc ('\r');
+
+ /* check THRE bit, wait for transmiter available */
+ for (i = 1; i < 3500; i++) {
+ if ((in8 (UART0_BASE + UART_LSR) & 0x20) == 0x20)
+ break;
+ udelay (100);
+ }
+ out8 (UART0_BASE + UART_THR, c); /* put character out */
}
-void
-serial_puts (const char *s)
+void serial_puts (const char *s)
{
- while (*s)
- {
- serial_putc (*s++);
- }
+ while (*s) {
+ serial_putc (*s++);
+ }
}
-int serial_getc()
+int serial_getc ()
{
- unsigned char status=0;
+ unsigned char status = 0;
- while(1) {
+ while (1) {
#if defined(CONFIG_HW_WATCHDOG)
- WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */
-#endif /* CONFIG_HW_WATCHDOG*/
- status = in8(UART0_BASE + UART_LSR);
- if ((status&asyncLSRDataReady1)!=0x0)
- {
- break;
- }
- else if ((status&(asyncLSRFramingError1|asyncLSROverrunError1|
- asyncLSRParityError1|asyncLSRBreakInterrupt1))!=0)
- {
- out8(UART0_BASE + UART_LSR, asyncLSRFramingError1|asyncLSROverrunError1|
- asyncLSRParityError1|asyncLSRBreakInterrupt1);
- }
- }
- return(0x000000ff&(int)in8(UART0_BASE));
+ WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
+#endif /* CONFIG_HW_WATCHDOG */
+ status = in8 (UART0_BASE + UART_LSR);
+ if ((status & asyncLSRDataReady1) != 0x0) {
+ break;
+ }
+ if ((status & ( asyncLSRFramingError1 |
+ asyncLSROverrunError1 |
+ asyncLSRParityError1 |
+ asyncLSRBreakInterrupt1 )) != 0) {
+ out8 (UART0_BASE + UART_LSR,
+ asyncLSRFramingError1 |
+ asyncLSROverrunError1 |
+ asyncLSRParityError1 |
+ asyncLSRBreakInterrupt1);
+ }
+ }
+ return (0x000000ff & (int) in8 (UART0_BASE));
}
-int
-serial_tstc()
+int serial_tstc ()
{
- unsigned char status;
-
- status = in8(UART0_BASE + UART_LSR);
- if ((status&asyncLSRDataReady1)!=0x0)
- {
- return(1);
- }
- if ((status&(asyncLSRFramingError1|asyncLSROverrunError1|asyncLSRParityError1|
- asyncLSRBreakInterrupt1))!=0)
- {
- out8(UART0_BASE + UART_LSR, asyncLSRFramingError1|asyncLSROverrunError1|
- asyncLSRParityError1|asyncLSRBreakInterrupt1);
- }
- return 0;
+ unsigned char status;
+
+ status = in8 (UART0_BASE + UART_LSR);
+ if ((status & asyncLSRDataReady1) != 0x0) {
+ return (1);
+ }
+ if ((status & ( asyncLSRFramingError1 |
+ asyncLSROverrunError1 |
+ asyncLSRParityError1 |
+ asyncLSRBreakInterrupt1 )) != 0) {
+ out8 (UART0_BASE + UART_LSR,
+ asyncLSRFramingError1 |
+ asyncLSROverrunError1 |
+ asyncLSRParityError1 |
+ asyncLSRBreakInterrupt1);
+ }
+ return 0;
}
#if CONFIG_SERIAL_SOFTWARE_FIFO
-void serial_isr(void *arg)
+void serial_isr (void *arg)
{
- int space;
- int c;
- const int rx_get = buf_info.rx_get;
- int rx_put = buf_info.rx_put;
-
- if (rx_get <= rx_put) {
- space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
- } else {
- space = rx_get - rx_put;
- }
- while (serial_tstc()) {
- c = serial_getc();
- if (space) {
- buf_info.rx_buffer[rx_put++] = c;
- space--;
- }
- if (rx_put==CONFIG_SERIAL_SOFTWARE_FIFO) rx_put = 0;
- if ( space < CONFIG_SERIAL_SOFTWARE_FIFO/4 ) {
- /* Stop flow by setting RTS inactive */
- out8(UART0_BASE + UART_MCR, in8(UART0_BASE + UART_MCR) & (0xFF^0x02));
- }
- }
- buf_info.rx_put = rx_put;
+ int space;
+ int c;
+ const int rx_get = buf_info.rx_get;
+ int rx_put = buf_info.rx_put;
+
+ if (rx_get <= rx_put) {
+ space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
+ } else {
+ space = rx_get - rx_put;
+ }
+ while (serial_tstc ()) {
+ c = serial_getc ();
+ if (space) {
+ buf_info.rx_buffer[rx_put++] = c;
+ space--;
+ }
+ if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
+ rx_put = 0;
+ if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
+ /* Stop flow by setting RTS inactive */
+ out8 (UART0_BASE + UART_MCR,
+ in8 (UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
+ }
+ }
+ buf_info.rx_put = rx_put;
}
-void
-serial_buffered_init (void)
+void serial_buffered_init (void)
{
- serial_puts( "Switching to interrupt driven serial input mode.\n" );
- buf_info.rx_buffer = malloc(CONFIG_SERIAL_SOFTWARE_FIFO);
- buf_info.rx_put = 0;
- buf_info.rx_get = 0;
-
- if (in8(UART0_BASE + UART_MSR) & 0x10) {
- serial_puts( "Check CTS signal present on serial port: OK.\n" );
- } else {
- serial_puts( "WARNING: CTS signal not present on serial port.\n" );
- }
-
- irq_install_handler(0/*UART0*/ /*int vec*/, serial_isr /*interrupt_handler_t *handler*/, (void*) &buf_info /*void *arg*/);
-
- /* Enable "RX Data Available" Interrupt on UART */
- /* out8(UART0_BASE + UART_IER, in8(UART0_BASE + UART_IER) |0x01); */
- out8(UART0_BASE + UART_IER, 0x01);
- /* Set DTR active */
- out8(UART0_BASE + UART_MCR, in8(UART0_BASE + UART_MCR) | 0x01);
- /* Start flow by setting RTS active */
- out8(UART0_BASE + UART_MCR, in8(UART0_BASE + UART_MCR) | 0x02);
- /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
- out8(UART0_BASE + UART_FCR, (1<<6)|1);
+ serial_puts ("Switching to interrupt driven serial input mode.\n");
+ buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
+ buf_info.rx_put = 0;
+ buf_info.rx_get = 0;
+
+ if (in8 (UART0_BASE + UART_MSR) & 0x10) {
+ serial_puts ("Check CTS signal present on serial port: OK.\n");
+ } else {
+ serial_puts ("WARNING: CTS signal not present on serial port.\n");
+ }
+
+ irq_install_handler (0 /*UART0 *//*int vec */ ,
+ serial_isr /*interrupt_handler_t *handler */ ,
+ (void *) &buf_info /*void *arg */ );
+
+ /* Enable "RX Data Available" Interrupt on UART */
+ /* out8(UART0_BASE + UART_IER, in8(UART0_BASE + UART_IER) |0x01); */
+ out8 (UART0_BASE + UART_IER, 0x01);
+ /* Set DTR active */
+ out8 (UART0_BASE + UART_MCR, in8 (UART0_BASE + UART_MCR) | 0x01);
+ /* Start flow by setting RTS active */
+ out8 (UART0_BASE + UART_MCR, in8 (UART0_BASE + UART_MCR) | 0x02);
+ /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
+ out8 (UART0_BASE + UART_FCR, (1 << 6) | 1);
}
-void
-serial_buffered_putc (const char c)
+void serial_buffered_putc (const char c)
{
- /* Wait for CTS */
+ /* Wait for CTS */
#if defined(CONFIG_HW_WATCHDOG)
- while (!(in8(UART0_BASE + UART_MSR) & 0x10))
- WATCHDOG_RESET();
+ while (!(in8 (UART0_BASE + UART_MSR) & 0x10))
+ WATCHDOG_RESET ();
#else
- while (!(in8(UART0_BASE + UART_MSR) & 0x10))
- ;
+ while (!(in8 (UART0_BASE + UART_MSR) & 0x10));
#endif
- serial_putc(c);
+ serial_putc (c);
}
-void
-serial_buffered_puts (const char *s)
+void serial_buffered_puts (const char *s)
{
- serial_puts(s);
+ serial_puts (s);
}
-int
-serial_buffered_getc (void)
+int serial_buffered_getc (void)
{
- int space;
- int c;
- int rx_get = buf_info.rx_get;
- int rx_put;
+ int space;
+ int c;
+ int rx_get = buf_info.rx_get;
+ int rx_put;
+
#if defined(CONFIG_HW_WATCHDOG)
- while (rx_get == buf_info.rx_put)
- WATCHDOG_RESET();
+ while (rx_get == buf_info.rx_put)
+ WATCHDOG_RESET ();
#else
- while (rx_get == buf_info.rx_put) ;
+ while (rx_get == buf_info.rx_put);
#endif
- c = buf_info.rx_buffer[rx_get++];
- if (rx_get==CONFIG_SERIAL_SOFTWARE_FIFO) rx_get = 0;
- buf_info.rx_get = rx_get;
-
- rx_put = buf_info.rx_put;
- if (rx_get <= rx_put) {
- space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
- } else {
- space = rx_get - rx_put;
- }
- if ( space > CONFIG_SERIAL_SOFTWARE_FIFO/2) {
- /* Start flow by setting RTS active */
- out8(UART0_BASE + UART_MCR, in8(UART0_BASE + UART_MCR) | 0x02);
- }
-
- return c;
+ c = buf_info.rx_buffer[rx_get++];
+ if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
+ rx_get = 0;
+ buf_info.rx_get = rx_get;
+
+ rx_put = buf_info.rx_put;
+ if (rx_get <= rx_put) {
+ space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
+ } else {
+ space = rx_get - rx_put;
+ }
+ if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
+ /* Start flow by setting RTS active */
+ out8 (UART0_BASE + UART_MCR, in8 (UART0_BASE + UART_MCR) | 0x02);
+ }
+
+ return c;
}
-int
-serial_buffered_tstc (void)
+int serial_buffered_tstc (void)
{
- return (buf_info.rx_get != buf_info.rx_put)?1:0;
+ return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
}
-#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
+#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
*/
#if (CONFIG_KGDB_SER_INDEX & 2)
-void
-kgdb_serial_init(void)
+void kgdb_serial_init (void)
{
- volatile char val;
- unsigned short br_reg;
- ulong cpu_clk;
-
- cpu_clk = get_gclk_freq ();
- br_reg = (((((cpu_clk/16)/18) * 10) / CONFIG_KGDB_BAUDRATE) + 5) / 10 ;
- /*
- * Init onboard 16550 UART
- */
- out8(UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
- out8(UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
- out8(UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
- out8(UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
- out8(UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
- out8(UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
- val = in8(UART1_BASE + UART_LSR); /* clear line status */
- val = in8(UART1_BASE + UART_RBR); /* read receive buffer */
- out8(UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
- out8(UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
+ volatile char val;
+ unsigned short br_reg;
+ ulong cpu_clk;
+
+ cpu_clk = get_gclk_freq ();
+ br_reg = (((((cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
+ 5) / 10;
+ /*
+ * Init onboard 16550 UART
+ */
+ out8 (UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
+ out8 (UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
+ out8 (UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
+ out8 (UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
+ out8 (UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
+ out8 (UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
+ val = in8 (UART1_BASE + UART_LSR); /* clear line status */
+ val = in8 (UART1_BASE + UART_RBR); /* read receive buffer */
+ out8 (UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
+ out8 (UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
}
-void putDebugChar
-(const char c)
+void putDebugChar (const char c)
{
- if (c == '\n')
- serial_putc ('\r');
+ if (c == '\n')
+ serial_putc ('\r');
- out8(UART1_BASE + UART_THR, c); /* put character out */
+ out8 (UART1_BASE + UART_THR, c); /* put character out */
- /* check THRE bit, wait for transfer done */
- while ((in8(UART1_BASE + UART_LSR) & 0x20) != 0x20)
- ;
+ /* check THRE bit, wait for transfer done */
+ while ((in8 (UART1_BASE + UART_LSR) & 0x20) != 0x20);
}
-void
-putDebugStr (const char *s)
+void putDebugStr (const char *s)
{
- while (*s)
- {
- serial_putc (*s++);
- }
+ while (*s) {
+ serial_putc (*s++);
+ }
}
-int
-getDebugChar(void)
+int getDebugChar (void)
{
- unsigned char status=0;
-
- while(1)
- {
- status = in8(UART1_BASE + UART_LSR);
- if ((status&asyncLSRDataReady1)!=0x0)
- {
- break;
- }
- else if ((status&(asyncLSRFramingError1|asyncLSROverrunError1|
- asyncLSRParityError1|asyncLSRBreakInterrupt1))!=0)
- {
- out8(UART1_BASE + UART_LSR, asyncLSRFramingError1|asyncLSROverrunError1|
- asyncLSRParityError1|asyncLSRBreakInterrupt1);
- }
- }
- return(0x000000ff&(int)in8(UART1_BASE));
+ unsigned char status = 0;
+
+ while (1) {
+ status = in8 (UART1_BASE + UART_LSR);
+ if ((status & asyncLSRDataReady1) != 0x0) {
+ break;
+ }
+ if ((status & ( asyncLSRFramingError1 |
+ asyncLSROverrunError1 |
+ asyncLSRParityError1 |
+ asyncLSRBreakInterrupt1 )) != 0) {
+ out8 (UART1_BASE + UART_LSR,
+ asyncLSRFramingError1 |
+ asyncLSROverrunError1 |
+ asyncLSRParityError1 |
+ asyncLSRBreakInterrupt1);
+ }
+ }
+ return (0x000000ff & (int) in8 (UART1_BASE));
}
-void
-kgdb_interruptible(int yes)
+void kgdb_interruptible (int yes)
{
-return;
+ return;
}
-#else
+#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
-void
-kgdb_serial_init(void)
+void kgdb_serial_init (void)
{
- serial_printf("[on serial] ");
+ serial_printf ("[on serial] ");
}
-void
-putDebugChar (int c)
+void putDebugChar (int c)
{
serial_putc (c);
}
-void
-putDebugStr (const char *str)
+void putDebugStr (const char *str)
{
serial_puts (str);
}
-int
-getDebugChar (void)
+int getDebugChar (void)
{
- return serial_getc();
+ return serial_getc ();
}
-void
-kgdb_interruptible (int yes)
+void kgdb_interruptible (int yes)
{
return;
}
-#endif
-#endif /* CFG_CMD_KGDB */
+#endif /* (CONFIG_KGDB_SER_INDEX & 2) */
+#endif /* CFG_CMD_KGDB */
-#endif /* CONFIG_405GP || CONFIG_405CR */
+#endif /* CONFIG_405GP || CONFIG_405CR */
projects / users / rw / ppcboot.git / commitdiff