void afu_release_irqs(struct cxl_context *ctx, void *cookie);
 void afu_irq_name_free(struct cxl_context *ctx);
 
-int cxl_attach_afu_directed_psl(struct cxl_context *ctx, u64 wed, u64 amr);
-int cxl_activate_dedicated_process_psl(struct cxl_afu *afu);
-int cxl_attach_dedicated_process_psl(struct cxl_context *ctx, u64 wed, u64 amr);
-void cxl_update_dedicated_ivtes_psl(struct cxl_context *ctx);
+int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
+int cxl_activate_dedicated_process_psl8(struct cxl_afu *afu);
+int cxl_attach_dedicated_process_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
+void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx);
 
 #ifdef CONFIG_DEBUG_FS
 
 void cxl_debugfs_adapter_remove(struct cxl *adapter);
 int cxl_debugfs_afu_add(struct cxl_afu *afu);
 void cxl_debugfs_afu_remove(struct cxl_afu *afu);
-void cxl_stop_trace_psl(struct cxl *cxl);
-void cxl_debugfs_add_adapter_regs_psl(struct cxl *adapter, struct dentry *dir);
+void cxl_stop_trace_psl8(struct cxl *cxl);
+void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter, struct dentry *dir);
 void cxl_debugfs_add_adapter_regs_xsl(struct cxl *adapter, struct dentry *dir);
-void cxl_debugfs_add_afu_regs_psl(struct cxl_afu *afu, struct dentry *dir);
+void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir);
 
 #else /* CONFIG_DEBUG_FS */
 
 {
 }
 
-static inline void cxl_stop_trace(struct cxl *cxl)
+static inline void cxl_stop_trace_psl8(struct cxl *cxl)
 {
 }
 
-static inline void cxl_debugfs_add_adapter_regs_psl(struct cxl *adapter,
+static inline void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter,
                                                    struct dentry *dir)
 {
 }
 {
 }
 
-static inline void cxl_debugfs_add_afu_regs_psl(struct cxl_afu *afu, struct dentry *dir)
+static inline void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir)
 {
 }
 
 };
 
 void cxl_assign_psn_space(struct cxl_context *ctx);
-int cxl_invalidate_all_psl(struct cxl *adapter);
-irqreturn_t cxl_irq_psl(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
+int cxl_invalidate_all_psl8(struct cxl *adapter);
+irqreturn_t cxl_irq_psl8(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
 irqreturn_t cxl_fail_irq_psl(struct cxl_afu *afu, struct cxl_irq_info *irq_info);
 int cxl_register_one_irq(struct cxl *adapter, irq_handler_t handler,
                        void *cookie, irq_hw_number_t *dest_hwirq,
 int cxl_afu_disable(struct cxl_afu *afu);
 int cxl_psl_purge(struct cxl_afu *afu);
 
-void cxl_native_irq_dump_regs_psl(struct cxl_context *ctx);
+void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx);
 void cxl_native_err_irq_dump_regs(struct cxl *adapter);
 int cxl_pci_vphb_add(struct cxl_afu *afu);
 void cxl_pci_vphb_remove(struct cxl_afu *afu);
 
 
 static struct dentry *cxl_debugfs;
 
-void cxl_stop_trace_psl(struct cxl *adapter)
+void cxl_stop_trace_psl8(struct cxl *adapter)
 {
        int slice;
 
                                          (void __force *)value, &fops_io_x64);
 }
 
-void cxl_debugfs_add_adapter_regs_psl(struct cxl *adapter, struct dentry *dir)
+void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter, struct dentry *dir)
 {
        debugfs_create_io_x64("fir1", S_IRUSR, dir, _cxl_p1_addr(adapter, CXL_PSL_FIR1));
        debugfs_create_io_x64("fir2", S_IRUSR, dir, _cxl_p1_addr(adapter, CXL_PSL_FIR2));
        debugfs_remove_recursive(adapter->debugfs);
 }
 
-void cxl_debugfs_add_afu_regs_psl(struct cxl_afu *afu, struct dentry *dir)
+void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir)
 {
        debugfs_create_io_x64("fir", S_IRUSR, dir, _cxl_p1n_addr(afu, CXL_PSL_FIR_SLICE_An));
        debugfs_create_io_x64("serr", S_IRUSR, dir, _cxl_p1n_addr(afu, CXL_PSL_SERR_An));
 
        }
 }
 
-int cxl_invalidate_all_psl(struct cxl *adapter)
+int cxl_invalidate_all_psl8(struct cxl *adapter)
 {
        unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
 
                WARN_ON(add_process_element(ctx));
 }
 
-int cxl_attach_afu_directed_psl(struct cxl_context *ctx, u64 wed, u64 amr)
+int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr)
 {
        u32 pid;
        int result;
        return 0;
 }
 
-int cxl_activate_dedicated_process_psl(struct cxl_afu *afu)
+int cxl_activate_dedicated_process_psl8(struct cxl_afu *afu)
 {
        dev_info(&afu->dev, "Activating dedicated process mode\n");
 
        return cxl_chardev_d_afu_add(afu);
 }
 
-void cxl_update_dedicated_ivtes_psl(struct cxl_context *ctx)
+void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx)
 {
        struct cxl_afu *afu = ctx->afu;
 
                        ((u64)ctx->irqs.range[3] & 0xffff));
 }
 
-int cxl_attach_dedicated_process_psl(struct cxl_context *ctx, u64 wed, u64 amr)
+int cxl_attach_dedicated_process_psl8(struct cxl_context *ctx, u64 wed, u64 amr)
 {
        struct cxl_afu *afu = ctx->afu;
        u64 pid;
        return 0;
 }
 
-void cxl_native_irq_dump_regs_psl(struct cxl_context *ctx)
+void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx)
 {
        u64 fir1, fir2, fir_slice, serr, afu_debug;
 
 
        return 0;
 }
 
-static int init_implementation_adapter_regs_psl(struct cxl *adapter, struct pci_dev *dev)
+static int init_implementation_adapter_regs_psl8(struct cxl *adapter, struct pci_dev *dev)
 {
        u64 psl_dsnctl, psl_fircntl;
        u64 chipid;
 /* For the PSL this is a multiple for 0 < n <= 7: */
 #define PSL_2048_250MHZ_CYCLES 1
 
-static void write_timebase_ctrl_psl(struct cxl *adapter)
+static void write_timebase_ctrl_psl8(struct cxl *adapter)
 {
        cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
                     TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
                     TBSYNC_CNT(XSL_4000_CLOCKS));
 }
 
-static u64 timebase_read_psl(struct cxl *adapter)
+static u64 timebase_read_psl8(struct cxl *adapter)
 {
        return cxl_p1_read(adapter, CXL_PSL_Timebase);
 }
        return;
 }
 
-static int init_implementation_afu_regs_psl(struct cxl_afu *afu)
+static int init_implementation_afu_regs_psl8(struct cxl_afu *afu)
 {
        /* read/write masks for this slice */
        cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
        return 0;
 }
 
-static int sanitise_afu_regs_psl(struct cxl_afu *afu)
+static int sanitise_afu_regs_psl8(struct cxl_afu *afu)
 {
        u64 reg;
 
        pci_disable_device(pdev);
 }
 
-static const struct cxl_service_layer_ops psl_ops = {
-       .adapter_regs_init = init_implementation_adapter_regs_psl,
-       .invalidate_all = cxl_invalidate_all_psl,
-       .afu_regs_init = init_implementation_afu_regs_psl,
-       .sanitise_afu_regs = sanitise_afu_regs_psl,
+static const struct cxl_service_layer_ops psl8_ops = {
+       .adapter_regs_init = init_implementation_adapter_regs_psl8,
+       .invalidate_all = cxl_invalidate_all_psl8,
+       .afu_regs_init = init_implementation_afu_regs_psl8,
+       .sanitise_afu_regs = sanitise_afu_regs_psl8,
        .register_serr_irq = cxl_native_register_serr_irq,
        .release_serr_irq = cxl_native_release_serr_irq,
-       .handle_interrupt = cxl_irq_psl,
+       .handle_interrupt = cxl_irq_psl8,
        .fail_irq = cxl_fail_irq_psl,
-       .activate_dedicated_process = cxl_activate_dedicated_process_psl,
-       .attach_afu_directed = cxl_attach_afu_directed_psl,
-       .attach_dedicated_process = cxl_attach_dedicated_process_psl,
-       .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl,
-       .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl,
-       .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl,
-       .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl,
+       .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
+       .attach_afu_directed = cxl_attach_afu_directed_psl8,
+       .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
+       .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
+       .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl8,
+       .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl8,
+       .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl8,
        .err_irq_dump_registers = cxl_native_err_irq_dump_regs,
-       .debugfs_stop_trace = cxl_stop_trace_psl,
-       .write_timebase_ctrl = write_timebase_ctrl_psl,
-       .timebase_read = timebase_read_psl,
+       .debugfs_stop_trace = cxl_stop_trace_psl8,
+       .write_timebase_ctrl = write_timebase_ctrl_psl8,
+       .timebase_read = timebase_read_psl8,
        .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
        .needs_reset_before_disable = true,
 };
 
 static const struct cxl_service_layer_ops xsl_ops = {
        .adapter_regs_init = init_implementation_adapter_regs_xsl,
-       .invalidate_all = cxl_invalidate_all_psl,
-       .sanitise_afu_regs = sanitise_afu_regs_psl,
-       .handle_interrupt = cxl_irq_psl,
+       .invalidate_all = cxl_invalidate_all_psl8,
+       .sanitise_afu_regs = sanitise_afu_regs_psl8,
+       .handle_interrupt = cxl_irq_psl8,
        .fail_irq = cxl_fail_irq_psl,
-       .activate_dedicated_process = cxl_activate_dedicated_process_psl,
-       .attach_afu_directed = cxl_attach_afu_directed_psl,
-       .attach_dedicated_process = cxl_attach_dedicated_process_psl,
-       .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl,
+       .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
+       .attach_afu_directed = cxl_attach_afu_directed_psl8,
+       .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
+       .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
        .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_xsl,
        .write_timebase_ctrl = write_timebase_ctrl_xsl,
        .timebase_read = timebase_read_xsl,
                adapter->native->sl_ops = &xsl_ops;
                adapter->min_pe = 1; /* Workaround for CX-4 hardware bug */
        } else {
-               dev_info(&dev->dev, "Device uses a PSL\n");
-               adapter->native->sl_ops = &psl_ops;
+               dev_info(&dev->dev, "Device uses a PSL8\n");
+               adapter->native->sl_ops = &psl8_ops;
        }
 }