void r100_bm_disable(struct radeon_device *rdev)
 {
        u32 tmp;
-       u16 tmp16;
 
        /* disable bus mastering */
        tmp = RREG32(R_000030_BUS_CNTL);
        WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
        tmp = RREG32(RADEON_BUS_CNTL);
        mdelay(1);
-       pci_read_config_word(rdev->pdev, 0x4, &tmp16);
-       pci_write_config_word(rdev->pdev, 0x4, tmp16 & 0xFFFB);
+       pci_clear_master(rdev->pdev);
        mdelay(1);
 }
 
 
        }
 }
 
-void rs600_bm_disable(struct radeon_device *rdev)
-{
-       u16 tmp;
-
-       /* disable bus mastering */
-       pci_read_config_word(rdev->pdev, 0x4, &tmp);
-       pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
-       mdelay(1);
-}
-
 int rs600_asic_reset(struct radeon_device *rdev)
 {
        struct rv515_mc_save save;
        WREG32(RADEON_CP_RB_CNTL, tmp);
        pci_save_state(rdev->pdev);
        /* disable bus mastering */
-       rs600_bm_disable(rdev);
+       pci_clear_master(rdev->pdev);
+       mdelay(1);
        /* reset GA+VAP */
        WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
                                        S_0000F0_SOFT_RESET_GA(1));