if (IS_CHERRYVIEW(dev_priv))
                        lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
 
-               vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
-                                   lane_mask);
+               vlv_wait_port_ready(display, dp_to_dig_port(intel_dp), lane_mask);
        }
 
        intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
 
                                const struct intel_crtc_state *pipe_config,
                                const struct drm_connector_state *conn_state)
 {
+       struct intel_display *display = to_intel_display(encoder);
        struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
-       struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
        vlv_phy_pre_encoder_enable(encoder, pipe_config);
 
 
        g4x_hdmi_enable_port(encoder, pipe_config);
 
-       vlv_wait_port_ready(dev_priv, dig_port, 0x0);
+       vlv_wait_port_ready(display, dig_port, 0x0);
 }
 
 static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
                                const struct intel_crtc_state *pipe_config,
                                const struct drm_connector_state *conn_state)
 {
+       struct intel_display *display = to_intel_display(encoder);
        struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
-       struct drm_device *dev = encoder->base.dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
 
        chv_phy_pre_encoder_enable(encoder, pipe_config);
 
 
        g4x_hdmi_enable_port(encoder, pipe_config);
 
-       vlv_wait_port_ready(dev_priv, dig_port, 0x0);
+       vlv_wait_port_ready(display, dig_port, 0x0);
 
        /* Second common lane will stay alive on its own now */
        chv_phy_release_cl2_override(encoder);
 
                assert_plane_disabled(plane);
 }
 
-void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
+void vlv_wait_port_ready(struct intel_display *display,
                         struct intel_digital_port *dig_port,
                         unsigned int expected_mask)
 {
                fallthrough;
        case PORT_B:
                port_mask = DPLL_PORTB_READY_MASK;
-               dpll_reg = DPLL(dev_priv, 0);
+               dpll_reg = DPLL(display, 0);
                break;
        case PORT_C:
                port_mask = DPLL_PORTC_READY_MASK;
-               dpll_reg = DPLL(dev_priv, 0);
+               dpll_reg = DPLL(display, 0);
                expected_mask <<= 4;
                break;
        case PORT_D:
                break;
        }
 
-       if (intel_de_wait(dev_priv, dpll_reg, port_mask, expected_mask, 1000))
-               drm_WARN(&dev_priv->drm, 1,
+       if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000))
+               drm_WARN(display->drm, 1,
                         "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
                         dig_port->base.base.base.id, dig_port->base.base.name,
-                        intel_de_read(dev_priv, dpll_reg) & port_mask,
+                        intel_de_read(display, dpll_reg) & port_mask,
                         expected_mask);
 }
 
 
 enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder);
 
 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
-void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
+void vlv_wait_port_ready(struct intel_display *display,
                         struct intel_digital_port *dig_port,
                         unsigned int expected_mask);