drm/meson: add RDMA module driver

The VPU embeds a "Register DMA" that can write a sequence of registers
on the VPU AHB bus, either manually or triggered by an internal IRQ
event like VSYNC or a line input counter.

The initial implementation handles a single channel (over 8), triggered
by the VSYNC irq and does not handle the RDMA irq.

The RDMA will be usefull to reset and program the AFBC decoder unit
on each vsync without involving the interrupt handler that can
be masked for a log period of time, producing display glitches.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-5-narmstrong@baylibre.com

diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile
index c389e2399133231d6664ba12c0d32c153e106b22..fb7f5440fe571c547dfc7ecdb8e14f7f9f0a6b01 100644 (file)
--- a/drivers/gpu/drm/meson/Makefile
+++ b/drivers/gpu/drm/meson/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 meson-drm-y := meson_drv.o meson_plane.o meson_crtc.o meson_venc_cvbs.o
 meson-drm-y += meson_viu.o meson_vpp.o meson_venc.o meson_vclk.o meson_overlay.o
+meson-drm-y += meson_rdma.o
 
 obj-$(CONFIG_DRM_MESON) += meson-drm.o
 obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o

diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h
index 3287282450a9c8d9a1e73ee0010e684412be635d..ea39be913c0f423e2696a129075ba1ced9bc7a55 100644 (file)
--- a/drivers/gpu/drm/meson/meson_drv.h
+++ b/drivers/gpu/drm/meson/meson_drv.h
@@ -123,6 +123,12 @@ struct meson_drm {
                bool venc_repeat;
                bool hdmi_use_enci;
        } venc;
+
+       struct {
+               dma_addr_t addr_phys;
+               uint32_t *addr;
+               unsigned int offset;
+       } rdma;
 };
 
 static inline int meson_vpu_is_compatible(struct meson_drm *priv,

diff --git a/drivers/gpu/drm/meson/meson_rdma.c b/drivers/gpu/drm/meson/meson_rdma.c
new file mode 100644 (file)
index 0000000..25b34b1
--- /dev/null
+++ b/drivers/gpu/drm/meson/meson_rdma.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/dma-mapping.h>
+
+#include "meson_drv.h"
+#include "meson_registers.h"
+#include "meson_rdma.h"
+
+/*
+ * The VPU embeds a "Register DMA" that can write a sequence of registers
+ * on the VPU AHB bus, either manually or triggered by an internal IRQ
+ * event like VSYNC or a line input counter.
+ * The initial implementation handles a single channel (over 8), triggered
+ * by the VSYNC irq and does not handle the RDMA irq.
+ */
+
+#define RDMA_DESC_SIZE (sizeof(uint32_t) * 2)
+
+int meson_rdma_init(struct meson_drm *priv)
+{
+       if (!priv->rdma.addr) {
+               /* Allocate a PAGE buffer */
+               priv->rdma.addr =
+                       dma_alloc_coherent(priv->dev, SZ_4K,
+                                          &priv->rdma.addr_phys,
+                                          GFP_KERNEL);
+               if (!priv->rdma.addr)
+                       return -ENOMEM;
+       }
+
+       priv->rdma.offset = 0;
+
+       writel_relaxed(RDMA_CTRL_SW_RESET,
+                      priv->io_base + _REG(RDMA_CTRL));
+       writel_relaxed(RDMA_DEFAULT_CONFIG |
+                      FIELD_PREP(RDMA_CTRL_AHB_WR_BURST, 3) |
+                      FIELD_PREP(RDMA_CTRL_AHB_RD_BURST, 0),
+                      priv->io_base + _REG(RDMA_CTRL));
+
+       return 0;
+}
+
+void meson_rdma_free(struct meson_drm *priv)
+{
+       if (!priv->rdma.addr && !priv->rdma.addr_phys)
+               return;
+
+       meson_rdma_stop(priv);
+
+       dma_free_coherent(priv->dev, SZ_4K,
+                         priv->rdma.addr, priv->rdma.addr_phys);
+
+       priv->rdma.addr = NULL;
+       priv->rdma.addr_phys = (dma_addr_t)NULL;
+}
+
+void meson_rdma_setup(struct meson_drm *priv)
+{
+       /* Channel 1: Write Flag, No Address Increment */
+       writel_bits_relaxed(RDMA_ACCESS_RW_FLAG_CHAN1 |
+                           RDMA_ACCESS_ADDR_INC_CHAN1,
+                           RDMA_ACCESS_RW_FLAG_CHAN1,
+                           priv->io_base + _REG(RDMA_ACCESS_AUTO));
+}
+
+void meson_rdma_stop(struct meson_drm *priv)
+{
+       writel_bits_relaxed(RDMA_IRQ_CLEAR_CHAN1,
+                           RDMA_IRQ_CLEAR_CHAN1,
+                           priv->io_base + _REG(RDMA_CTRL));
+
+       /* Stop Channel 1 */
+       writel_bits_relaxed(RDMA_ACCESS_TRIGGER_CHAN1,
+                           FIELD_PREP(RDMA_ACCESS_ADDR_INC_CHAN1,
+                                      RDMA_ACCESS_TRIGGER_STOP),
+                           priv->io_base + _REG(RDMA_ACCESS_AUTO));
+}
+
+void meson_rdma_reset(struct meson_drm *priv)
+{
+       meson_rdma_stop(priv);
+
+       priv->rdma.offset = 0;
+}
+
+static void meson_rdma_writel(struct meson_drm *priv, uint32_t val,
+                             uint32_t reg)
+{
+       if (priv->rdma.offset >= (SZ_4K / RDMA_DESC_SIZE)) {
+               dev_warn_once(priv->dev, "%s: overflow\n", __func__);
+               return;
+       }
+
+       priv->rdma.addr[priv->rdma.offset++] = reg;
+       priv->rdma.addr[priv->rdma.offset++] = val;
+}
+
+/*
+ * This will add the register to the RDMA buffer and write it to the
+ * hardware at the same time.
+ * When meson_rdma_flush is called, the RDMA will replay the register
+ * writes in order.
+ */
+void meson_rdma_writel_sync(struct meson_drm *priv, uint32_t val, uint32_t reg)
+{
+       meson_rdma_writel(priv, val, reg);
+
+       writel_relaxed(val, priv->io_base + _REG(reg));
+}
+
+void meson_rdma_flush(struct meson_drm *priv)
+{
+       meson_rdma_stop(priv);
+
+       /* Start of Channel 1 register writes buffer */
+       writel(priv->rdma.addr_phys,
+              priv->io_base + _REG(RDMA_AHB_START_ADDR_1));
+
+       /* Last byte on Channel 1 register writes buffer */
+       writel(priv->rdma.addr_phys + (priv->rdma.offset * RDMA_DESC_SIZE) - 1,
+              priv->io_base + _REG(RDMA_AHB_END_ADDR_1));
+
+       /* Trigger Channel 1 on VSYNC event */
+       writel_bits_relaxed(RDMA_ACCESS_TRIGGER_CHAN1,
+                           FIELD_PREP(RDMA_ACCESS_TRIGGER_CHAN1,
+                                      RDMA_ACCESS_TRIGGER_VSYNC),
+                           priv->io_base + _REG(RDMA_ACCESS_AUTO));
+
+       priv->rdma.offset = 0;
+}

diff --git a/drivers/gpu/drm/meson/meson_rdma.h b/drivers/gpu/drm/meson/meson_rdma.h
new file mode 100644 (file)
index 0000000..3870bff
--- /dev/null
+++ b/drivers/gpu/drm/meson/meson_rdma.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef __MESON_RDMA_H
+#define __MESON_RDMA_H
+
+#include "meson_drv.h"
+
+int meson_rdma_init(struct meson_drm *priv);
+void meson_rdma_free(struct meson_drm *priv);
+void meson_rdma_setup(struct meson_drm *priv);
+void meson_rdma_reset(struct meson_drm *priv);
+void meson_rdma_stop(struct meson_drm *priv);
+
+void meson_rdma_writel_sync(struct meson_drm *priv, uint32_t val, uint32_t reg);
+void meson_rdma_flush(struct meson_drm *priv);
+
+#endif /* __MESON_RDMA_H */