Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
                        ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
                        ib_size_alignment = 1;
                        break;
+               case AMDGPU_HW_IP_UVD_ENC:
+                       type = AMD_IP_BLOCK_TYPE_UVD;
+                       for (i = 0; i < adev->uvd.num_enc_rings; i++)
+                               ring_mask |= ((adev->uvd.ring_enc[i].ready ? 1 : 0) << i);
+                       ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
+                       ib_size_alignment = 1;
+                       break;
                default:
                        return -EINVAL;
                }
                case AMDGPU_HW_IP_VCE:
                        type = AMD_IP_BLOCK_TYPE_VCE;
                        break;
+               case AMDGPU_HW_IP_UVD_ENC:
+                       type = AMD_IP_BLOCK_TYPE_UVD;
+                       break;
                default:
                        return -EINVAL;
                }