compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
                        clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
-                                <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
+                                <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
+                                <&zs_clk>;
                        #clock-cells = <1>;
                        clock-indices = <
                                R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
-                               R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER
+                               R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
+                               R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
                                R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
                        >;
                        clock-output-names =
-                               "mlb", "vin3", "vin2", "vin1", "vin0", "ether",
-                               "sata1", "sata0";
+                               "mlb", "vin3", "vin2", "vin1", "vin0",
+                               "etheravb", "ether", "sata1", "sata0";
                };
                mstp9_clks: mstp9_clks@e6150994 {
                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 
 #define R8A7790_CLK_VIN2               9
 #define R8A7790_CLK_VIN1               10
 #define R8A7790_CLK_VIN0               11
+#define R8A7790_CLK_ETHERAVB           12
 #define R8A7790_CLK_ETHER              13
 #define R8A7790_CLK_SATA1              14
 #define R8A7790_CLK_SATA0              15