drm/amd/display: Add link encoding to timing BW calculation parameters

[Why]
There certain cases where the timing BW is dependent on the type of link
encoding in use. Thus to calculate the correct BW required for a given
timing, the link encoding should be added as a parameter.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 44ea0da56374b8326f97f932cb69a8c9f9b00fa1..70fd0a2e8bdb7cbb76ea76968ac0b24a3bf38202 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5793,6 +5793,7 @@ static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
                                edp_min_bpp_x16, edp_max_bpp_x16,
                                dsc_caps,
                                &stream->timing,
+                               dc_link_get_highest_encoding_format(aconnector->dc_link),
                                &bw_range)) {
 
                if (bw_range.max_kbps < link_bw_in_kbps) {
@@ -5801,6 +5802,7 @@ static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
                                        &dsc_options,
                                        0,
                                        &stream->timing,
+                                       dc_link_get_highest_encoding_format(aconnector->dc_link),
                                        &dsc_cfg)) {
                                stream->timing.dsc_cfg = dsc_cfg;
                                stream->timing.flags.DSC = 1;
@@ -5815,6 +5817,7 @@ static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
                                &dsc_options,
                                link_bw_in_kbps,
                                &stream->timing,
+                               dc_link_get_highest_encoding_format(aconnector->dc_link),
                                &dsc_cfg)) {
                stream->timing.dsc_cfg = dsc_cfg;
                stream->timing.flags.DSC = 1;
@@ -5858,12 +5861,14 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
                                                &dsc_options,
                                                link_bandwidth_kbps,
                                                &stream->timing,
+                                               dc_link_get_highest_encoding_format(aconnector->dc_link),
                                                &stream->timing.dsc_cfg)) {
                                stream->timing.flags.DSC = 1;
                                DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
                        }
                } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
-                       timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
+                       timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
+                                       dc_link_get_highest_encoding_format(aconnector->dc_link));
                        max_supported_bw_in_kbps = link_bandwidth_kbps;
                        dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
 
@@ -5875,6 +5880,7 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
                                                &dsc_options,
                                                dsc_max_supported_bw_in_kbps,
                                                &stream->timing,
+                                               dc_link_get_highest_encoding_format(aconnector->dc_link),
                                                &stream->timing.dsc_cfg)) {
                                        stream->timing.flags.DSC = 1;
                                        DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 1d343f16e5b8f362e165fc4723f7bd640c1cf5c7..1abdec14344e80333e8c2f6a8f8698e5197b68b0 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -828,6 +828,7 @@ static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *p
                                        &dsc_options,
                                        0,
                                        params[i].timing,
+                                       dc_link_get_highest_encoding_format(params[i].aconnector->dc_link),
                                        &params[i].timing->dsc_cfg)) {
                        params[i].timing->flags.DSC = 1;
 
@@ -878,7 +879,9 @@ static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
                        param.sink->ctx->dc->res_pool->dscs[0],
                        &param.sink->dsc_caps.dsc_dec_caps,
                        &dsc_options,
-                       (int) kbps, param.timing, &dsc_config);
+                       (int) kbps, param.timing,
+                       dc_link_get_highest_encoding_format(param.aconnector->dc_link),
+                       &dsc_config);
 
        return dsc_config.bits_per_pixel;
 }
@@ -1116,8 +1119,11 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
                                dsc_policy.min_target_bpp * 16,
                                dsc_policy.max_target_bpp * 16,
                                &stream->sink->dsc_caps.dsc_dec_caps,
-                               &stream->timing, &params[count].bw_range))
-                       params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
+                               &stream->timing,
+                               dc_link_get_highest_encoding_format(dc_link),
+                               &params[count].bw_range))
+                       params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
+                                       dc_link_get_highest_encoding_format(dc_link));
 
                count++;
        }
@@ -1577,7 +1583,7 @@ static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
                                       dsc_policy.min_target_bpp * 16,
                                       dsc_policy.max_target_bpp * 16,
                                       &stream->sink->dsc_caps.dsc_dec_caps,
-                                      &stream->timing, bw_range);
+                                      &stream->timing, dc_link_get_highest_encoding_format(stream->link), bw_range);
 
        return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16;
 }

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
index 18e098568cb468bd0d1806e1533376bd427a3e96..0d19d4cd191659eae0a62453f6db614e3808471f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
@@ -314,6 +314,24 @@ const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link)
        return link->dc->link_srv->dp_get_verified_link_cap(link);
 }
 
+enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link)
+{
+       if (dc_is_dp_signal(link->connector_signal)) {
+               if (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_DVI_DONGLE &&
+                               link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE)
+                       return DC_LINK_ENCODING_HDMI_TMDS;
+               else if (link->dc->link_srv->dp_get_encoding_format(&link->verified_link_cap) ==
+                               DP_8b_10b_ENCODING)
+                       return DC_LINK_ENCODING_DP_8b_10b;
+               else if (link->dc->link_srv->dp_get_encoding_format(&link->verified_link_cap) ==
+                               DP_128b_132b_ENCODING)
+                       return DC_LINK_ENCODING_DP_128b_132b;
+       } else if (dc_is_hdmi_signal(link->connector_signal)) {
+       }
+
+       return DC_LINK_ENCODING_UNSPECIFIED;
+}
+
 bool dc_link_is_dp_sink_present(struct dc_link *link)
 {
        return link->dc->link_srv->dp_is_sink_present(link);

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 8a317b7717f780b34a075e5177d1ec6447fbd6f7..d265ef8543c861e4864e39ba44b5239bc97b11f1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1415,7 +1415,9 @@ void dc_set_disable_128b_132b_stream_overhead(bool disable);
 /* The function returns minimum bandwidth required to drive a given timing
  * return - minimum required timing bandwidth in kbps.
  */
-uint32_t dc_bandwidth_in_kbps_from_timing(const struct dc_crtc_timing *timing);
+uint32_t dc_bandwidth_in_kbps_from_timing(
+               const struct dc_crtc_timing *timing,
+               const enum dc_link_encoding_format link_encoding);
 
 /* Link Interfaces */
 /*
@@ -1853,6 +1855,14 @@ enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format(
  */
 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link);
 
+/* Get the highest encoding format that the link supports; highest meaning the
+ * encoding format which supports the maximum bandwidth.
+ *
+ * @link - a link with DP RX connection
+ * return - highest encoding format link supports.
+ */
+enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link);
+
 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected
  * to a link with dp connector signal type.
  * @link - a link with dp connector signal type

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
index 9491b76d61f58f572a3c4a48100d082a5d3045bc..fe3078b8789ef142ea4e3eb9b1c6792ac3aea5cb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -73,6 +73,7 @@ bool dc_dsc_compute_bandwidth_range(
                uint32_t max_bpp_x16,
                const struct dsc_dec_dpcd_caps *dsc_sink_caps,
                const struct dc_crtc_timing *timing,
+               const enum dc_link_encoding_format link_encoding,
                struct dc_dsc_bw_range *range);
 
 bool dc_dsc_compute_config(
@@ -81,6 +82,7 @@ bool dc_dsc_compute_config(
                const struct dc_dsc_config_options *options,
                uint32_t target_bandwidth_kbps,
                const struct dc_crtc_timing *timing,
+               const enum dc_link_encoding_format link_encoding,
                struct dc_dsc_config *dsc_cfg);
 
 uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing,

diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index ed4c1744dcbe0b9855ec800be83ab3954b4b881e..14d7804b70b28733273c4e37128a2c131f1027e4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -878,7 +878,7 @@ struct dsc_dec_dpcd_caps {
        uint32_t branch_overall_throughput_0_mps; /* In MPs */
        uint32_t branch_overall_throughput_1_mps; /* In MPs */
        uint32_t branch_max_line_width;
-       bool is_dp;
+       bool is_dp; /* Decoded format */
 };
 
 struct dc_golden_table {
@@ -901,6 +901,14 @@ enum dc_gpu_mem_alloc_type {
        DC_MEM_ALLOC_TYPE_AGP
 };
 
+enum dc_link_encoding_format {
+       DC_LINK_ENCODING_UNSPECIFIED = 0,
+       DC_LINK_ENCODING_DP_8b_10b,
+       DC_LINK_ENCODING_DP_128b_132b,
+       DC_LINK_ENCODING_HDMI_TMDS,
+       DC_LINK_ENCODING_HDMI_FRL
+};
+
 enum dc_psr_version {
        DC_PSR_VERSION_1                        = 0,
        DC_PSR_VERSION_SU_1                     = 1,

diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index aed0d3dafa2472684a97a573e4701fd0f53a1921..3966845c769453888675b80c32ede95c0b62fa5f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -85,7 +85,8 @@ static uint32_t apply_128b_132b_stream_overhead(
 }
 
 uint32_t dc_bandwidth_in_kbps_from_timing(
-       const struct dc_crtc_timing *timing)
+       const struct dc_crtc_timing *timing,
+       const enum dc_link_encoding_format link_encoding)
 {
        uint32_t bits_per_channel = 0;
        uint32_t kbps;
@@ -133,6 +134,9 @@ uint32_t dc_bandwidth_in_kbps_from_timing(
                        kbps = kbps * 2 / 3;
        }
 
+       if (link_encoding == DC_LINK_ENCODING_DP_128b_132b)
+               kbps = apply_128b_132b_stream_overhead(timing, kbps);
+
        return kbps;
 }
 
@@ -144,6 +148,7 @@ static bool decide_dsc_bandwidth_range(
                const uint32_t num_slices_h,
                const struct dsc_enc_caps *dsc_caps,
                const struct dc_crtc_timing *timing,
+               const enum dc_link_encoding_format link_encoding,
                struct dc_dsc_bw_range *range);
 
 static uint32_t compute_bpp_x16_from_target_bandwidth(
@@ -170,6 +175,7 @@ static bool setup_dsc_config(
                int target_bandwidth_kbps,
                const struct dc_crtc_timing *timing,
                const struct dc_dsc_config_options *options,
+               const enum dc_link_encoding_format link_encoding,
                struct dc_dsc_config *dsc_cfg);
 
 static bool dsc_buff_block_size_from_dpcd(int dpcd_buff_block_size, int *buff_block_size)
@@ -435,6 +441,7 @@ bool dc_dsc_compute_bandwidth_range(
                uint32_t max_bpp_x16,
                const struct dsc_dec_dpcd_caps *dsc_sink_caps,
                const struct dc_crtc_timing *timing,
+               const enum dc_link_encoding_format link_encoding,
                struct dc_dsc_bw_range *range)
 {
        bool is_dsc_possible = false;
@@ -454,11 +461,11 @@ bool dc_dsc_compute_bandwidth_range(
 
        if (is_dsc_possible)
                is_dsc_possible = setup_dsc_config(dsc_sink_caps, &dsc_enc_caps, 0, timing,
-                               &options, &config);
+                               &options, link_encoding, &config);
 
        if (is_dsc_possible)
                is_dsc_possible = decide_dsc_bandwidth_range(min_bpp_x16, max_bpp_x16,
-                               config.num_slices_h, &dsc_common_caps, timing, range);
+                               config.num_slices_h, &dsc_common_caps, timing, link_encoding, range);
 
        return is_dsc_possible;
 }
@@ -594,6 +601,7 @@ static bool decide_dsc_bandwidth_range(
                const uint32_t num_slices_h,
                const struct dsc_enc_caps *dsc_caps,
                const struct dc_crtc_timing *timing,
+               const enum dc_link_encoding_format link_encoding,
                struct dc_dsc_bw_range *range)
 {
        uint32_t preferred_bpp_x16 = timing->dsc_fixed_bits_per_pixel_x16;
@@ -623,7 +631,7 @@ static bool decide_dsc_bandwidth_range(
        /* populate output structure */
        if (range->max_target_bpp_x16 >= range->min_target_bpp_x16 && range->min_target_bpp_x16 > 0) {
                /* native stream bandwidth */
-               range->stream_kbps = dc_bandwidth_in_kbps_from_timing(timing);
+               range->stream_kbps = dc_bandwidth_in_kbps_from_timing(timing, link_encoding);
 
                /* max dsc target bpp */
                range->max_kbps = dc_dsc_stream_bandwidth_in_kbps(timing,
@@ -649,6 +657,7 @@ static bool decide_dsc_target_bpp_x16(
                const int target_bandwidth_kbps,
                const struct dc_crtc_timing *timing,
                const int num_slices_h,
+               const enum dc_link_encoding_format link_encoding,
                int *target_bpp_x16)
 {
        struct dc_dsc_bw_range range;
@@ -656,7 +665,7 @@ static bool decide_dsc_target_bpp_x16(
        *target_bpp_x16 = 0;
 
        if (decide_dsc_bandwidth_range(policy->min_target_bpp * 16, policy->max_target_bpp * 16,
-                       num_slices_h, dsc_common_caps, timing, &range)) {
+                       num_slices_h, dsc_common_caps, timing, link_encoding, &range)) {
                if (target_bandwidth_kbps >= range.stream_kbps) {
                        if (policy->enable_dsc_when_not_needed)
                                /* enable max bpp even dsc is not needed */
@@ -833,6 +842,7 @@ static bool setup_dsc_config(
                int target_bandwidth_kbps,
                const struct dc_crtc_timing *timing,
                const struct dc_dsc_config_options *options,
+               const enum dc_link_encoding_format link_encoding,
                struct dc_dsc_config *dsc_cfg)
 {
        struct dsc_enc_caps dsc_common_caps;
@@ -1032,6 +1042,7 @@ static bool setup_dsc_config(
                                target_bandwidth_kbps,
                                timing,
                                num_slices_h,
+                               link_encoding,
                                &target_bpp);
                dsc_cfg->bits_per_pixel = target_bpp;
        }
@@ -1060,6 +1071,7 @@ bool dc_dsc_compute_config(
                const struct dc_dsc_config_options *options,
                uint32_t target_bandwidth_kbps,
                const struct dc_crtc_timing *timing,
+               const enum dc_link_encoding_format link_encoding,
                struct dc_dsc_config *dsc_cfg)
 {
        bool is_dsc_possible = false;
@@ -1069,7 +1081,7 @@ bool dc_dsc_compute_config(
        is_dsc_possible = setup_dsc_config(dsc_sink_caps,
                &dsc_enc_caps,
                target_bandwidth_kbps,
-               timing, options, dsc_cfg);
+               timing, options, link_encoding, dsc_cfg);
        return is_dsc_possible;
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index 834f34249af00102e38b014302cf56039d8b3f25..7997936613fc35a4416e55520a267e2b16db0d36 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -1079,8 +1079,14 @@ static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
 {
        uint64_t kbps;
+       enum dc_link_encoding_format link_encoding;
 
-       kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
+       if (dp_is_128b_132b_signal(pipe_ctx))
+               link_encoding = DC_LINK_ENCODING_DP_128b_132b;
+       else
+               link_encoding = DC_LINK_ENCODING_DP_8b_10b;
+
+       kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding);
        return get_pbn_from_bw_in_kbps(kbps);
 }
 
@@ -1538,7 +1544,8 @@ struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp(
                        dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT);
        struct fixed31_32 timing_bw =
                        dc_fixpt_from_int(
-                                       dc_bandwidth_in_kbps_from_timing(&stream->timing));
+                                       dc_bandwidth_in_kbps_from_timing(&stream->timing,
+                                                       dc_link_get_highest_encoding_format(link)));
        struct fixed31_32 avg_time_slots_per_mtp =
                        dc_fixpt_div(timing_bw, timeslot_bw_effective);
 

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
index e8b2fc4002a52d07dc91e7cee0c3250acd23dc51..b45fda96eaf649bf16f291df2294d787680e0287 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
@@ -130,7 +130,8 @@ static bool dp_active_dongle_validate_timing(
                                /* DP input has DSC, HDMI FRL output doesn't have DSC, remove DSC from output timing */
                                outputTiming.flags.DSC = 0;
 #endif
-                       if (dc_bandwidth_in_kbps_from_timing(&outputTiming) > dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps)
+                       if (dc_bandwidth_in_kbps_from_timing(&outputTiming, DC_LINK_ENCODING_HDMI_FRL) >
+                                       dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps)
                                return false;
                } else { // DP to HDMI TMDS converter
                        if (get_tmds_output_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
@@ -285,7 +286,7 @@ static bool dp_validate_mode_timing(
                link_setting = &link->verified_link_cap;
        */
 
-       req_bw = dc_bandwidth_in_kbps_from_timing(timing);
+       req_bw = dc_bandwidth_in_kbps_from_timing(timing, dc_link_get_highest_encoding_format(link));
        max_bw = dp_link_bandwidth_kbps(link, link_setting);
 
        if (req_bw <= max_bw) {
@@ -357,7 +358,8 @@ bool link_validate_dpia_bandwidth(const struct dc_stream_state *stream, const un
        for (uint8_t i = 0; i < num_streams; ++i) {
 
                link[i] = stream[i].link;
-               bw_needed[i] = dc_bandwidth_in_kbps_from_timing(&stream[i].timing);
+               bw_needed[i] = dc_bandwidth_in_kbps_from_timing(&stream[i].timing,
+                               dc_link_get_highest_encoding_format(link[i]));
        }
 
        ret = dpia_validate_usb4_bw(link, bw_needed, num_streams);

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index 03aae0c250227cb4d6f9e5c5c7015ad101a5cdd3..b38ac3ea06b0f094b8da4ae2e2c400db30c38fb5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -906,7 +906,7 @@ bool link_decide_link_settings(struct dc_stream_state *stream,
        struct dc_link_settings *link_setting)
 {
        struct dc_link *link = stream->link;
-       uint32_t req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
+       uint32_t req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, dc_link_get_highest_encoding_format(link));
 
        memset(link_setting, 0, sizeof(*link_setting));
 
@@ -939,7 +939,8 @@ bool link_decide_link_settings(struct dc_stream_state *stream,
 
                                tmp_link_setting.link_rate = LINK_RATE_UNKNOWN;
                                tmp_timing.flags.DSC = 0;
-                               orig_req_bw = dc_bandwidth_in_kbps_from_timing(&tmp_timing);
+                               orig_req_bw = dc_bandwidth_in_kbps_from_timing(&tmp_timing,
+                                               dc_link_get_highest_encoding_format(link));
                                edp_decide_link_settings(link, &tmp_link_setting, orig_req_bw);
                                max_link_rate = tmp_link_setting.link_rate;
                        }

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
index e011df4bdaf216a872a6c6fee711faaed645e523..90339c2dfd84871bfc15a4169b20c01b7687aa97 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
@@ -1699,13 +1699,20 @@ bool perform_link_training_with_retries(
                } else if (do_fallback) { /* Try training at lower link bandwidth if doing fallback. */
                        uint32_t req_bw;
                        uint32_t link_bw;
+                       enum dc_link_encoding_format link_encoding = DC_LINK_ENCODING_UNSPECIFIED;
 
                        decide_fallback_link_setting(link, &max_link_settings,
                                        &cur_link_settings, status);
+
+                       if (link_dp_get_encoding_format(&cur_link_settings) == DP_8b_10b_ENCODING)
+                               link_encoding = DC_LINK_ENCODING_DP_8b_10b;
+                       else if (link_dp_get_encoding_format(&cur_link_settings) == DP_128b_132b_ENCODING)
+                               link_encoding = DC_LINK_ENCODING_DP_128b_132b;
+
                        /* Flag if reduced link bandwidth no longer meets stream requirements or fallen back to
                         * minimum link bandwidth.
                         */
-                       req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
+                       req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, link_encoding);
                        link_bw = dp_link_bandwidth_kbps(link, &cur_link_settings);
                        is_link_bw_low = (req_bw > link_bw);
                        is_link_bw_min = ((cur_link_settings.link_rate <= LINK_RATE_LOW) &&

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index 69fdd6e142d6e6479c73437097b6280205b5eebb..92f58a719c07996dfcb1266631d626dab20fed77 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -320,7 +320,7 @@ bool edp_is_ilr_optimization_required(struct dc_link *link,
        core_link_read_dpcd(link, DP_LANE_COUNT_SET,
                                &lane_count_set.raw, sizeof(lane_count_set));
 
-       req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing);
+       req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing, dc_link_get_highest_encoding_format(link));
 
        if (!crtc_timing->flags.DSC)
                edp_decide_link_settings(link, &link_setting, req_bw);