* system clock, and have no internal clock divider.
                 */
 
-               if (WARN_ON(!rcrtc->extclock))
-                       return;
-
                /*
                 * The H3 ES1.x exhibits dot clock duty cycle stability issues.
                 * We can work around them by configuring the DPLL to twice the
        clk = devm_clk_get(rcdu->dev, clk_name);
        if (!IS_ERR(clk)) {
                rcrtc->extclock = clk;
-       } else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) {
-               dev_info(rcdu->dev, "can't get external clock %u\n", hwindex);
+       } else if (PTR_ERR(clk) == -EPROBE_DEFER) {
                return -EPROBE_DEFER;
+       } else if (rcdu->info->dpll_mask & BIT(hwindex)) {
+               /*
+                * DU channels that have a display PLL can't use the internal
+                * system clock and thus require an external clock.
+                */
+               ret = PTR_ERR(clk);
+               dev_err(rcdu->dev, "can't get dclkin.%u: %d\n", hwindex, ret);
+               return ret;
        }
 
        init_waitqueue_head(&rcrtc->flip_wait);