drm/amd/display: create DCN3-specific log for MPC state

Logging DCN3 MPC state was following DCN1 implementation that doesn't
consider new DCN3 MPC color blocks. Create new elements according to
DCN3 MPC color caps and a new DCN3-specific function for reading MPC
data.

v3:
- remove gamut remap reg reading in favor of fixed31_32 matrix data

Signed-off-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
index a6a4c3413f895b50d86fc22d81977801221aef22..bf3386cd444d62c5232909f9b88061e6abf98887 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
@@ -1440,8 +1440,54 @@ static void mpc3_set_mpc_mem_lp_mode(struct mpc *mpc)
        }
 }
 
+static void mpc3_read_mpcc_state(
+               struct mpc *mpc,
+               int mpcc_inst,
+               struct mpcc_state *s)
+{
+       struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+       uint32_t rmu_status = 0xf;
+
+       REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id);
+       REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id);
+       REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id);
+       REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,
+                       MPCC_ALPHA_BLND_MODE, &s->alpha_mode,
+                       MPCC_ALPHA_MULTIPLIED_MODE, &s->pre_multiplied_alpha,
+                       MPCC_BLND_ACTIVE_OVERLAP_ONLY, &s->overlap_only);
+       REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
+                       MPCC_BUSY, &s->busy);
+
+       /* Color blocks state */
+       REG_GET(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, &rmu_status);
+
+       if (rmu_status == mpcc_inst) {
+               REG_GET(SHAPER_CONTROL[0],
+                       MPC_RMU_SHAPER_LUT_MODE_CURRENT, &s->shaper_lut_mode);
+               REG_GET(RMU_3DLUT_MODE[0],
+                       MPC_RMU_3DLUT_MODE_CURRENT,  &s->lut3d_mode);
+               REG_GET(RMU_3DLUT_READ_WRITE_CONTROL[0],
+                       MPC_RMU_3DLUT_30BIT_EN, &s->lut3d_bit_depth);
+               REG_GET(RMU_3DLUT_MODE[0],
+                       MPC_RMU_3DLUT_SIZE, &s->lut3d_size);
+       } else {
+               REG_GET(SHAPER_CONTROL[1],
+                       MPC_RMU_SHAPER_LUT_MODE_CURRENT, &s->shaper_lut_mode);
+               REG_GET(RMU_3DLUT_MODE[1],
+                       MPC_RMU_3DLUT_MODE_CURRENT,  &s->lut3d_mode);
+               REG_GET(RMU_3DLUT_READ_WRITE_CONTROL[1],
+                       MPC_RMU_3DLUT_30BIT_EN, &s->lut3d_bit_depth);
+               REG_GET(RMU_3DLUT_MODE[1],
+                       MPC_RMU_3DLUT_SIZE, &s->lut3d_size);
+       }
+
+        REG_GET_2(MPCC_OGAM_CONTROL[mpcc_inst],
+                 MPCC_OGAM_MODE_CURRENT, &s->rgam_mode,
+                 MPCC_OGAM_SELECT_CURRENT, &s->rgam_lut);
+}
+
 static const struct mpc_funcs dcn30_mpc_funcs = {
-       .read_mpcc_state = mpc1_read_mpcc_state,
+       .read_mpcc_state = mpc3_read_mpcc_state,
        .insert_plane = mpc1_insert_plane,
        .remove_mpcc = mpc1_remove_mpcc,
        .mpc_init = mpc1_mpc_init,

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
index 61a2406dcc53937ff38ce7996c761a1c82cb9deb..a11e40fddc44e2d4a1a1fce0a56799e767e3884f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -199,6 +199,13 @@ struct mpcc_state {
        uint32_t overlap_only;
        uint32_t idle;
        uint32_t busy;
+       uint32_t shaper_lut_mode;
+       uint32_t lut3d_mode;
+       uint32_t lut3d_bit_depth;
+       uint32_t lut3d_size;
+       uint32_t rgam_mode;
+       uint32_t rgam_lut;
+       struct mpc_grph_gamut_adjustment gamut_remap;
 };
 
 /**