ARM: dts: imx50: Align pin config nodes with bindings

Bindings expect pin configuration nodes in pinctrl to match certain
naming and not be part of another fake node:

pinctrl@30330000: '...' does not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'

Drop the wrapping node and adjust the names to have "grp" prefix.
Diff looks big but this should have no functional impact, use e.g.
git show -w to view the diff.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/nxp/imx/imx50-evk.dts b/arch/arm/boot/dts/nxp/imx/imx50-evk.dts
index 3f45c01d9cce39f8220c93ccd48ebf0e8e28d9e4..f40b0d5fdb85fdc1a4b9acb1c0a0f3d6f1e34b43 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx50-evk.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx50-evk.dts
@@ -52,40 +52,38 @@
 };
 
 &iomuxc {
-       imx50-evk {
-               pinctrl_cspi: cspigrp {
-                       fsl,pins = <
-                               MX50_PAD_CSPI_SCLK__CSPI_SCLK           0x00
-                               MX50_PAD_CSPI_MISO__CSPI_MISO           0x00
-                               MX50_PAD_CSPI_MOSI__CSPI_MOSI           0x00
-                               MX50_PAD_CSPI_SS0__GPIO4_11             0xc4
-                               MX50_PAD_ECSPI1_MOSI__GPIO4_13          0x84
-                       >;
-               };
+       pinctrl_cspi: cspigrp {
+               fsl,pins = <
+                       MX50_PAD_CSPI_SCLK__CSPI_SCLK           0x00
+                       MX50_PAD_CSPI_MISO__CSPI_MISO           0x00
+                       MX50_PAD_CSPI_MOSI__CSPI_MOSI           0x00
+                       MX50_PAD_CSPI_SS0__GPIO4_11             0xc4
+                       MX50_PAD_ECSPI1_MOSI__GPIO4_13          0x84
+               >;
+       };
 
-               pinctrl_fec: fecgrp {
-                       fsl,pins = <
-                               MX50_PAD_SSI_RXFS__FEC_MDC              0x80
-                               MX50_PAD_SSI_RXC__FEC_MDIO              0x80
-                               MX50_PAD_DISP_D0__FEC_TX_CLK            0x80
-                               MX50_PAD_DISP_D1__FEC_RX_ERR            0x80
-                               MX50_PAD_DISP_D2__FEC_RX_DV             0x80
-                               MX50_PAD_DISP_D3__FEC_RDATA_1           0x80
-                               MX50_PAD_DISP_D4__FEC_RDATA_0           0x80
-                               MX50_PAD_DISP_D5__FEC_TX_EN             0x80
-                               MX50_PAD_DISP_D6__FEC_TDATA_1           0x80
-                               MX50_PAD_DISP_D7__FEC_TDATA_0           0x80
-                       >;
-               };
+       pinctrl_fec: fecgrp {
+               fsl,pins = <
+                       MX50_PAD_SSI_RXFS__FEC_MDC              0x80
+                       MX50_PAD_SSI_RXC__FEC_MDIO              0x80
+                       MX50_PAD_DISP_D0__FEC_TX_CLK            0x80
+                       MX50_PAD_DISP_D1__FEC_RX_ERR            0x80
+                       MX50_PAD_DISP_D2__FEC_RX_DV             0x80
+                       MX50_PAD_DISP_D3__FEC_RDATA_1           0x80
+                       MX50_PAD_DISP_D4__FEC_RDATA_0           0x80
+                       MX50_PAD_DISP_D5__FEC_TX_EN             0x80
+                       MX50_PAD_DISP_D6__FEC_TDATA_1           0x80
+                       MX50_PAD_DISP_D7__FEC_TDATA_0           0x80
+               >;
+       };
 
-               pinctrl_uart1: uart1grp {
-                       fsl,pins = <
-                               MX50_PAD_UART1_TXD__UART1_TXD_MUX       0x1e4
-                               MX50_PAD_UART1_RXD__UART1_RXD_MUX       0x1e4
-                               MX50_PAD_UART1_RTS__UART1_RTS           0x1e4
-                               MX50_PAD_UART1_CTS__UART1_CTS           0x1e4
-                       >;
-               };
+       pinctrl_uart1: uart1grp {
+               fsl,pins = <
+                       MX50_PAD_UART1_TXD__UART1_TXD_MUX       0x1e4
+                       MX50_PAD_UART1_RXD__UART1_RXD_MUX       0x1e4
+                       MX50_PAD_UART1_RTS__UART1_RTS           0x1e4
+                       MX50_PAD_UART1_CTS__UART1_CTS           0x1e4
+               >;
        };
 };
 

diff --git a/arch/arm/boot/dts/nxp/imx/imx50.dtsi b/arch/arm/boot/dts/nxp/imx/imx50.dtsi
index c5b25d2f6264ae4e220924458cc713e6087418d5..1b6f444443dd1b191709235bf18fae8780fb7988 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx50.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx50.dtsi
@@ -283,7 +283,7 @@
                                clock-names = "ipg", "per";
                        };
 
-                       iomuxc: iomuxc@53fa8000 {
+                       iomuxc: pinctrl@53fa8000 {
                                compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
                                reg = <0x53fa8000 0x4000>;
                        };