drm/amdgpu: enable ASPM support for PCIE 7.4.0/7.6.0

Enable ASPM support for PCIE 7.4.0 and 7.6.0.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 47bcf86cd0f3fe73c9ebcfc9f4f448dfdec3b2b5..7971d9208ecf259b1b55362c6b49d0d7554f5d75 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -670,6 +670,7 @@ enum amd_hw_ip_block_type {
        RSMU_HWIP,
        XGMI_HWIP,
        DCI_HWIP,
+       PCIE_HWIP,
        MAX_HWIP
 };
 

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index b0811287f017f898826a1d73ead7686282397428..1369a1b74929a72a063a9abaee16033b5c9ddc45 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -194,6 +194,7 @@ static int hw_id_map[MAX_HWIP] = {
        [UMC_HWIP]      = UMC_HWID,
        [XGMI_HWIP]     = XGMI_HWID,
        [DCI_HWIP]      = DCI_HWID,
+       [PCIE_HWIP]     = PCIE_HWID,
 };
 
 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
index ed31d133f07ae9b976e3a6242124efc1fe4cc4b9..233be735165aa0d4ebfe72a30d836b4635855da5 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
@@ -344,6 +344,121 @@ static u32 nbio_v4_3_get_rom_offset(struct amdgpu_device *adev)
        return rom_offset;
 }
 
+#ifdef CONFIG_PCIEASPM
+static void nbio_v4_3_program_ltr(struct amdgpu_device *adev)
+{
+       uint32_t def, data;
+
+       def = RREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);
+       data = 0x35EB;
+       data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK;
+       data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK;
+       if (def != data)
+               WREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data);
+
+       def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2);
+       data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK;
+       if (def != data)
+               WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2, data);
+
+       def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
+       if (adev->pdev->ltr_path)
+               data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
+       else
+               data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
+       if (def != data)
+               WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
+}
+#endif
+
+static void nbio_v4_3_program_aspm(struct amdgpu_device *adev)
+{
+#ifdef CONFIG_PCIEASPM
+       uint32_t def, data;
+
+       if (!(adev->ip_versions[PCIE_HWIP][0] == IP_VERSION(7, 4, 0)) &&
+             !(adev->ip_versions[PCIE_HWIP][0] == IP_VERSION(7, 6, 0)))
+               return;
+
+       def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL);
+       data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
+       data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
+       data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
+       if (def != data)
+               WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL, data);
+
+       def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL7);
+       data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK;
+       if (def != data)
+               WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL7, data);
+
+       def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3);
+       data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
+       if (def != data)
+               WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3, data);
+
+       def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3);
+       data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK;
+       data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK;
+       if (def != data)
+               WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data);
+
+       def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5);
+       data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK;
+       if (def != data)
+               WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data);
+
+       def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
+       data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
+       if (def != data)
+               WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
+
+       WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001);
+
+       def = data = RREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2);
+       data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |
+               PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;
+       data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK;
+       if (def != data)
+               WREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2, data);
+
+       def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL4);
+       data |= PCIE_LC_CNTL4__LC_L1_POWERDOWN_MASK;
+       if (def != data)
+               WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL4, data);
+
+       def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL);
+       data |= PCIE_LC_RXRECOVER_RXSTANDBY_CNTL__LC_RX_L0S_STANDBY_EN_MASK;
+       if (def != data)
+               WREG32_SOC15(NBIO, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL, data);
+
+       nbio_v4_3_program_ltr(adev);
+
+       def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3);
+       data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;
+       data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT;
+       if (def != data)
+               WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data);
+
+       def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5);
+       data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT;
+       if (def != data)
+               WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data);
+
+       def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL);
+       data |= 0x0 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT;
+       data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
+       data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
+       if (def != data)
+               WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL, data);
+
+       def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3);
+       data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
+       if (def != data)
+               WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3, data);
+#endif
+}
+
 const struct amdgpu_nbio_funcs nbio_v4_3_funcs = {
        .get_hdp_flush_req_offset = nbio_v4_3_get_hdp_flush_req_offset,
        .get_hdp_flush_done_offset = nbio_v4_3_get_hdp_flush_done_offset,
@@ -365,4 +480,5 @@ const struct amdgpu_nbio_funcs nbio_v4_3_funcs = {
        .init_registers = nbio_v4_3_init_registers,
        .remap_hdp_registers = nbio_v4_3_remap_hdp_registers,
        .get_rom_offset = nbio_v4_3_get_rom_offset,
+       .program_aspm = nbio_v4_3_program_aspm,
 };

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 57eaafb70d7251b7a06b01d50b588ac8563c6f0c..495848515edfa2a4400d0b3bace9127786761139 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -386,11 +386,12 @@ static void soc21_pcie_gen3_enable(struct amdgpu_device *adev)
 
 static void soc21_program_aspm(struct amdgpu_device *adev)
 {
-
-       if (amdgpu_aspm == 0)
+       if (!amdgpu_device_should_use_aspm(adev))
                return;
 
-       /* todo */
+       if (!(adev->flags & AMD_IS_APU) &&
+           (adev->nbio.funcs->program_aspm))
+               adev->nbio.funcs->program_aspm(adev);
 }
 
 static void soc21_enable_doorbell_aperture(struct amdgpu_device *adev,

diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_offset.h
index 53802d674e13ee61c228683349a4a6bf5b04be74..4b489d64deaaecc1e32e08d0de4193bd3fdedd45 100644 (file)
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_offset.h
@@ -6918,6 +6918,8 @@
 #define regPSWUSCFG0_SSID_CAP                                                                           0x2880031
 #define regPSWUSCFG0_SSID_CAP_BASE_IDX                                                                  5
 
+#define regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL                                                             0x2890102
+#define regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL_BASE_IDX                                                    5
 
 // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
 // base address: 0x10100000

diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h
index f3cda48bfaeb3234abbbb6dc1ce4a4edbbb6bc14..d038fd915351ccb94832b9aef5f1f824b6e6145d 100644 (file)
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h
@@ -82045,5 +82045,6 @@
 #define BIF_CFG_DEV0_EPF3_1_RTR_DATA2__FLR_TIME_MASK                                                          0x00000FFFL
 #define BIF_CFG_DEV0_EPF3_1_RTR_DATA2__D3HOTD0_TIME_MASK                                                      0x00FFF000L
 
+#define PCIE_LC_RXRECOVER_RXSTANDBY_CNTL__LC_RX_L0S_STANDBY_EN_MASK                                           0x00010000L
 
 #endif