// SPDX-License-Identifier: GPL-2.0
 /*
- * Core functions for TI TPS65224/TPS6594/TPS6593/LP8764 PMICs
+ * Core functions for following TI PMICs:
+ *  - LP8764
+ *  - TPS65224
+ *  - TPS652G1
+ *  - TPS6593
+ *  - TPS6594
  *
  * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
  */
        TPS6594_REG_INT_FSM_ERR,
 };
 
+/* TPS652G1 Resources */
+
+static const struct mfd_cell tps652g1_common_cells[] = {
+       MFD_CELL_RES("tps6594-pfsm", tps65224_pfsm_resources),
+       MFD_CELL_RES("tps6594-pinctrl", tps65224_pinctrl_resources),
+       MFD_CELL_NAME("tps6594-regulator"),
+};
+
+static const struct regmap_irq tps652g1_irqs[] = {
+       /* INT_GPIO register */
+       REGMAP_IRQ_REG(TPS65224_IRQ_GPIO1, 2, TPS65224_BIT_GPIO1_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_GPIO2, 2, TPS65224_BIT_GPIO2_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_GPIO3, 2, TPS65224_BIT_GPIO3_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_GPIO4, 2, TPS65224_BIT_GPIO4_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_GPIO5, 2, TPS65224_BIT_GPIO5_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_GPIO6, 2, TPS65224_BIT_GPIO6_INT),
+
+       /* INT_STARTUP register */
+       REGMAP_IRQ_REG(TPS65224_IRQ_VSENSE, 3, TPS65224_BIT_VSENSE_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_ENABLE, 3, TPS6594_BIT_ENABLE_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_PB_SHORT, 3, TPS65224_BIT_PB_SHORT_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_FSD, 3, TPS6594_BIT_FSD_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_SOFT_REBOOT, 3, TPS6594_BIT_SOFT_REBOOT_INT),
+
+       /* INT_MISC register */
+       REGMAP_IRQ_REG(TPS65224_IRQ_BIST_PASS, 4, TPS6594_BIT_BIST_PASS_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_EXT_CLK, 4, TPS6594_BIT_EXT_CLK_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_REG_UNLOCK, 4, TPS65224_BIT_REG_UNLOCK_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_TWARN, 4, TPS6594_BIT_TWARN_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_PB_LONG, 4, TPS65224_BIT_PB_LONG_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_PB_FALL, 4, TPS65224_BIT_PB_FALL_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_PB_RISE, 4, TPS65224_BIT_PB_RISE_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_ADC_CONV_READY, 4, TPS65224_BIT_ADC_CONV_READY_INT),
+
+       /* INT_MODERATE_ERR register */
+       REGMAP_IRQ_REG(TPS65224_IRQ_TSD_ORD, 5, TPS6594_BIT_TSD_ORD_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_BIST_FAIL, 5, TPS6594_BIT_BIST_FAIL_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_REG_CRC_ERR, 5, TPS6594_BIT_REG_CRC_ERR_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_RECOV_CNT, 5, TPS6594_BIT_RECOV_CNT_INT),
+
+       /* INT_SEVERE_ERR register */
+       REGMAP_IRQ_REG(TPS65224_IRQ_TSD_IMM, 6, TPS6594_BIT_TSD_IMM_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_VCCA_OVP, 6, TPS6594_BIT_VCCA_OVP_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_PFSM_ERR, 6, TPS6594_BIT_PFSM_ERR_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_BG_XMON, 6, TPS65224_BIT_BG_XMON_INT),
+
+       /* INT_FSM_ERR register */
+       REGMAP_IRQ_REG(TPS65224_IRQ_IMM_SHUTDOWN, 7, TPS6594_BIT_IMM_SHUTDOWN_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_ORD_SHUTDOWN, 7, TPS6594_BIT_ORD_SHUTDOWN_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_MCU_PWR_ERR, 7, TPS6594_BIT_MCU_PWR_ERR_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_SOC_PWR_ERR, 7, TPS6594_BIT_SOC_PWR_ERR_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_COMM_ERR, 7, TPS6594_BIT_COMM_ERR_INT),
+       REGMAP_IRQ_REG(TPS65224_IRQ_I2C2_ERR, 7, TPS65224_BIT_I2C2_ERR_INT),
+};
+
 static inline unsigned int tps6594_get_irq_reg(struct regmap_irq_chip_data *data,
                                               unsigned int base, int index)
 {
         * a new interrupt.
         */
        if (tps->use_crc) {
-               if (tps->chip_id == TPS65224) {
+               if (tps->chip_id == TPS65224 || tps->chip_id == TPS652G1) {
                        regmap_reg = TPS6594_REG_INT_FSM_ERR;
                        mask_val = TPS6594_BIT_COMM_ERR_INT;
                } else {
        .handle_post_irq = tps6594_handle_post_irq,
 };
 
+static struct regmap_irq_chip tps652g1_irq_chip = {
+       .ack_base = TPS6594_REG_INT_BUCK,
+       .ack_invert = 1,
+       .clear_ack = 1,
+       .init_ack_masked = 1,
+       .num_regs = ARRAY_SIZE(tps65224_irq_reg),
+       .irqs = tps652g1_irqs,
+       .num_irqs = ARRAY_SIZE(tps652g1_irqs),
+       .get_irq_reg = tps65224_get_irq_reg,
+       .handle_post_irq = tps6594_handle_post_irq,
+};
+
 static const struct regmap_range tps6594_volatile_ranges[] = {
        regmap_reg_range(TPS6594_REG_INT_TOP, TPS6594_REG_STAT_READBACK_ERR),
        regmap_reg_range(TPS6594_REG_RTC_STATUS, TPS6594_REG_RTC_STATUS),
        int ret;
        unsigned int regmap_reg, mask_val;
 
-       if (tps->chip_id == TPS65224) {
+       if (tps->chip_id == TPS65224 || tps->chip_id == TPS652G1) {
                regmap_reg = TPS6594_REG_CONFIG_2;
                mask_val = TPS65224_BIT_I2C1_SPI_CRC_EN;
        } else {
        int ret;
        unsigned int regmap_reg, mask_val;
 
-       if (tps->chip_id == TPS65224) {
+       if (tps->chip_id == TPS65224 || tps->chip_id == TPS652G1) {
                regmap_reg = TPS6594_REG_CONFIG_2;
                mask_val = TPS65224_BIT_I2C1_SPI_CRC_EN;
        } else {
                irq_chip = &tps65224_irq_chip;
                n_cells = ARRAY_SIZE(tps65224_common_cells);
                cells = tps65224_common_cells;
+       } else if (tps->chip_id == TPS652G1) {
+               irq_chip = &tps652g1_irq_chip;
+               n_cells = ARRAY_SIZE(tps652g1_common_cells);
+               cells = tps652g1_common_cells;
        } else {
                irq_chip = &tps6594_irq_chip;
                n_cells = ARRAY_SIZE(tps6594_common_cells);
        if (ret)
                return dev_err_probe(dev, ret, "Failed to add common child devices\n");
 
-       /* No RTC for LP8764 and TPS65224 */
-       if (tps->chip_id != LP8764 && tps->chip_id != TPS65224) {
+       /* No RTC for LP8764, TPS65224 and TPS652G1 */
+       if (tps->chip_id != LP8764 && tps->chip_id != TPS65224 && tps->chip_id != TPS652G1) {
                ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, tps6594_rtc_cells,
                                           ARRAY_SIZE(tps6594_rtc_cells), NULL, 0,
                                           regmap_irq_get_domain(tps->irq_data));