media: ti-vpe: cal: Add CSI2 context

CAL has 8 CSI2 contexts per PHY, which are used to tag the incoming
data.  The current driver only uses the first context, but we need to
support all of them to implement multi-stream support.

Add a csi2_ctx field to cal_ctx, which indicates which of the 8 CSI2
contexts is used for the particular cal_ctx. Also clean up the context
register macros to take the CSI2 context number as a parameter.

Note that before this patch the CSI2 context used for both PHYs was
always 0. This patch always uses cal_ctx index number as the CSI2
context. There is no functional difference, but this approach will work
also in the future when we use more than 1 CSI2 context per PHY.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c
index fb3d14162ffa2fc105480568b04161f1b6d16191..a96019cf8b28546f3f88e2f77ca097f8955309a8 100644 (file)
--- a/drivers/media/platform/ti-vpe/cal.c
+++ b/drivers/media/platform/ti-vpe/cal.c
@@ -294,7 +294,7 @@ static void cal_ctx_csi2_config(struct cal_ctx *ctx)
 {
        u32 val;
 
-       val = cal_read(ctx->cal, CAL_CSI2_CTX0(ctx->index));
+       val = cal_read(ctx->cal, CAL_CSI2_CTX(ctx->phy->instance, ctx->csi2_ctx));
        cal_set_field(&val, ctx->cport, CAL_CSI2_CTX_CPORT_MASK);
        /*
         * DT type: MIPI CSI-2 Specs
@@ -310,9 +310,10 @@ static void cal_ctx_csi2_config(struct cal_ctx *ctx)
        cal_set_field(&val, CAL_CSI2_CTX_ATT_PIX, CAL_CSI2_CTX_ATT_MASK);
        cal_set_field(&val, CAL_CSI2_CTX_PACK_MODE_LINE,
                      CAL_CSI2_CTX_PACK_MODE_MASK);
-       cal_write(ctx->cal, CAL_CSI2_CTX0(ctx->index), val);
-       ctx_dbg(3, ctx, "CAL_CSI2_CTX0(%d) = 0x%08x\n", ctx->index,
-               cal_read(ctx->cal, CAL_CSI2_CTX0(ctx->index)));
+       cal_write(ctx->cal, CAL_CSI2_CTX(ctx->phy->instance, ctx->csi2_ctx), val);
+       ctx_dbg(3, ctx, "CAL_CSI2_CTX(%u, %u) = 0x%08x\n",
+               ctx->phy->instance, ctx->csi2_ctx,
+               cal_read(ctx->cal, CAL_CSI2_CTX(ctx->phy->instance, ctx->csi2_ctx)));
 }
 
 static void cal_ctx_pix_proc_config(struct cal_ctx *ctx)
@@ -853,6 +854,7 @@ static struct cal_ctx *cal_ctx_create(struct cal_dev *cal, int inst)
        ctx->cal = cal;
        ctx->phy = cal->phy[inst];
        ctx->index = inst;
+       ctx->csi2_ctx = inst;
        ctx->cport = inst;
 
        ret = cal_ctx_v4l2_init(ctx);

diff --git a/drivers/media/platform/ti-vpe/cal.h b/drivers/media/platform/ti-vpe/cal.h
index 251bb0ba7b3bc3717f1a21dcb720158052dcee23..bcc3378b6b41dd5707c5fcd7f1a9b65ad64c1659 100644 (file)
--- a/drivers/media/platform/ti-vpe/cal.h
+++ b/drivers/media/platform/ti-vpe/cal.h
@@ -219,6 +219,7 @@ struct cal_ctx {
        struct vb2_queue        vb_vidq;
        u8                      index;
        u8                      cport;
+       u8                      csi2_ctx;
 };
 
 extern unsigned int cal_debug;

diff --git a/drivers/media/platform/ti-vpe/cal_regs.h b/drivers/media/platform/ti-vpe/cal_regs.h
index f752096dcf7f7bd315895b4c842224aecca1c602..bf937919a1e96fbd63fe9c48572a52c4acf811cb 100644 (file)
--- a/drivers/media/platform/ti-vpe/cal_regs.h
+++ b/drivers/media/platform/ti-vpe/cal_regs.h
@@ -72,22 +72,8 @@
 #define CAL_CSI2_TIMING(m)             (0x314U + (m) * 0x80U)
 #define CAL_CSI2_VC_IRQENABLE(m)       (0x318U + (m) * 0x80U)
 #define CAL_CSI2_VC_IRQSTATUS(m)       (0x328U + (m) * 0x80U)
-#define CAL_CSI2_CTX0(m)               (0x330U + (m) * 0x80U)
-#define CAL_CSI2_CTX1(m)               (0x334U + (m) * 0x80U)
-#define CAL_CSI2_CTX2(m)               (0x338U + (m) * 0x80U)
-#define CAL_CSI2_CTX3(m)               (0x33cU + (m) * 0x80U)
-#define CAL_CSI2_CTX4(m)               (0x340U + (m) * 0x80U)
-#define CAL_CSI2_CTX5(m)               (0x344U + (m) * 0x80U)
-#define CAL_CSI2_CTX6(m)               (0x348U + (m) * 0x80U)
-#define CAL_CSI2_CTX7(m)               (0x34cU + (m) * 0x80U)
-#define CAL_CSI2_STATUS0(m)            (0x350U + (m) * 0x80U)
-#define CAL_CSI2_STATUS1(m)            (0x354U + (m) * 0x80U)
-#define CAL_CSI2_STATUS2(m)            (0x358U + (m) * 0x80U)
-#define CAL_CSI2_STATUS3(m)            (0x35cU + (m) * 0x80U)
-#define CAL_CSI2_STATUS4(m)            (0x360U + (m) * 0x80U)
-#define CAL_CSI2_STATUS5(m)            (0x364U + (m) * 0x80U)
-#define CAL_CSI2_STATUS6(m)            (0x368U + (m) * 0x80U)
-#define CAL_CSI2_STATUS7(m)            (0x36cU + (m) * 0x80U)
+#define CAL_CSI2_CTX(phy, csi2_ctx)    (0x330U + (phy) * 0x80U + (csi2_ctx) * 4)
+#define CAL_CSI2_STATUS(phy, csi2_ctx) (0x350U + (phy) * 0x80U + (csi2_ctx) * 4)
 
 /* CAL CSI2 PHY register offsets */
 #define CAL_CSI2_PHY_REG0              0x000