Modifications for 1.2.0:
======================================================================
+* Patch by Denis Peter, 29 Jul 2002:
+ - waits for ATA_STAT_DRQ instead for ATA_STAT_RDY in
+ ide_ident. This has two reasons:
+ 1. ATAPI devices doesn't set the RDY bit
+ 2. Only read the inquiry data if the drive is ready to transmit.
+ - added check powermode command, to check the powermode
+ of the connected drive. If the drive is in standby, the
+ IDE_SPIN_UP_TIME_OUT is used instead of the IDE_TIME_OUT.
+ - various fixes in the ATAPI part, to get more IDE CDROMs to work.
+ - fixes in cmd_ide.c and part_iso.c for CD boot
+ - added check powermode in cmd_ide.c to expand the IDE timeout
+ when the drive is in power-down.
+
+* Patch by Wolfgang Grandegger, 29 Jul 2002:
+ update for Siemens SCM board
+
* Patch by David Updegraff, 27 Jul 2002:
update for Cray L1 board
CCM_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx CCM siemens
-SCM_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx SCM siemens
-
cogent_mpc8xx_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx cogent
sbc8260_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8260 sbc8260
+SCM_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc8260 SCM siemens
+
TQM8260_config \
TQM8260_L2_config \
TQM8260_266MHz_config \
/* .. return NULL means it wasnt mine, non-null means I got it..*/
u8 *dhcp_vendorex_proc(u8 *pop)
{
-u8 oplen,*sub_op, sub_oplen,thing, *retval;
+u8 oplen,*sub_op, sub_oplen,thing = 0, *retval;
retval = NULL;
oplen = *(pop + 1);
#define KEYBD_CMD_READ_STATUS 0x03
#define KEYBD_CMD_RESET_ERRORS 0x10
+/* status codes */
+#define KEYBD_STATUS_MASK 0x3F
+
/* Number of bytes returned from Keyboard Controller */
#define KEYBD_VERSIONLEN 2 /* version information */
#define KEYBD_DATALEN 9 /* normal key scan data */
val = KEYBD_CMD_READ_STATUS;
i2c_write (kbd_addr, 0, 0, &val, 1);
i2c_read (kbd_addr, 0, 0, &errcd, 1);
+ errcd &= KEYBD_STATUS_MASK; /* clear unused bits */
if (errcd) {
printf ("KEYBD: Error %02X\n", errcd);
}
-
/* Reset error code and verify */
val = KEYBD_CMD_RESET_ERRORS;
i2c_write (kbd_addr, 0, 0, &val, 1);
i2c_write (kbd_addr, 0, 0, &val, 1);
i2c_read (kbd_addr, 0, 0, &val, 1);
- if (val) { /* permanent error, report it */
+ val &= KEYBD_STATUS_MASK; /* clear unused bits */
+ if (val) { /* permanent error, report it */
printf ("*** Keyboard error code %02X ***\n", val);
sprintf (keybd_env, "%02X", val);
setenv ("keybd", keybd_env);
static uchar *key_match (uchar * kbd_data)
{
- uchar compare[KEYBD_DATALEN];
+ uchar compare[KEYBD_DATALEN-1];
uchar magic[sizeof (kbd_magic_prefix) + 1];
uchar extra;
uchar *str, *nxt, *suffix;
#if 0
printf ("### Check magic \"%s\"\n", magic);
#endif
- memcpy (compare, kbd_data, KEYBD_DATALEN);
+ /* Don't include modifier byte */
+ memcpy (compare, kbd_data+1, KEYBD_DATALEN-1);
extra = 0;
* Set matches to zero, so they match only once
* and we can find duplicates or extra keys
*/
- for (k = 0; k < KEYBD_DATALEN; ++k) {
+ for (k = 0; k < sizeof(compare); ++k) {
if (compare[k] == '\0') /* only non-zero entries */
continue;
if (c == compare[k]) { /* found matching key */
break;
}
}
- if (k == KEYBD_DATALEN) {
+ if (k == sizeof(compare)) {
extra = 1; /* unmatched key */
}
}
* and has no extra keys
*/
- for (i = 0; i < KEYBD_DATALEN; ++i) {
+ for (i = 0; i < sizeof(compare); ++i) {
if (compare[i])
break;
}
- if ((i == KEYBD_DATALEN) && (extra == 0)) {
+ if ((i == sizeof(compare)) && (extra == 0)) {
uchar cmd_name[sizeof (kbd_command_prefix) + 1];
char *cmd;
/* if reset = 1 IDE reset will be asserted */
if(idereset)
out8(PLD_COM_MODE_REG,(in8(PLD_COM_MODE_REG)|0x1));
- else
+ else {
+ udelay(10000);
out8(PLD_COM_MODE_REG,(in8(PLD_COM_MODE_REG)&0xfe));
+ }
}
resreg = in8 (PLD_SCSI_RST_REG);
if (idereset == 1)
resreg |= 0x20;
- else
+ else {
+ udelay(10000);
resreg &= 0xdf;
+ }
out8 (PLD_SCSI_RST_REG, resreg);
}
LIB = lib$(BOARD).a
-OBJS = scm.o flash.o fpga_scm.o ../common/fpga.o \
+OBJS = scm.o flash.o fpga_scm.o ../common/fpga.o \
../../tqm8xx/load_sernum_ethaddr.o
fpga_t fpga_list[] = {
{ "FIOX" , CFG_FIOX_BASE ,
- CFG_PC_FIOX_INIT , CFG_PC_FIOX_PROG , CFG_PC_FIOX_DONE },
+ CFG_PD_FIOX_INIT , CFG_PD_FIOX_PROG , CFG_PD_FIOX_DONE },
{ "FDOHM", CFG_FDOHM_BASE,
- CFG_PC_FDOHM_INIT, CFG_PC_FDOHM_PROG, CFG_PC_FDOHM_DONE }
+ CFG_PD_FDOHM_INIT, CFG_PD_FDOHM_PROG, CFG_PD_FDOHM_DONE }
};
int fpga_count = sizeof(fpga_list) / sizeof(fpga_t);
ulong fpga_control (fpga_t* fpga, int cmd)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
switch (cmd) {
case FPGA_INIT_IS_HIGH:
return (immr->im_ioport.iop_pdatd & fpga->done_mask) ? 1:0;
case FPGA_READ_MODE:
-#if 0
- /* disable FPGA in memory controller */
- memctl->memc_br4 = 0;
- memctl->memc_or4 = PUMA_CONF_OR_READ;
- memctl->memc_br4 = PUMA_CONF_BR_READ;
-
- /* (re-) enable CAN drivers */
- can_driver_enable ();
-#endif
break;
case FPGA_LOAD_MODE:
-#if 0
- /* disable FPGA in memory controller */
- memctl->memc_br4 = 0;
- /*
- * We must disable the CAN drivers first because
- * they use UPM B, too.
- */
- can_driver_disable ();
- /*
- * Configure UPMB for FPGA
- */
- upmconfig(UPMB,(uint *)puma_table,sizeof(puma_table)/sizeof(uint));
- memctl->memc_or4 = PUMA_CONF_OR_LOAD;
- memctl->memc_br4 = PUMA_CONF_BR_LOAD;
-#endif
break;
case FPGA_GET_ID:
- if (fpga->conf_base == CFG_FIOX_BASE)
- return (*(volatile ulong *)(fpga->conf_base + 0x10) >> 18) & 0xff;
- else if (fpga->conf_base == CFG_FDOHM_BASE)
- return *(volatile ushort *)fpga->conf_base & 0xff;
- else
+ if (fpga->conf_base == CFG_FIOX_BASE) {
+ ulong ver = *(volatile ulong *)(fpga->conf_base + 0x10);
+ return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0);
+ }
+ else if (fpga->conf_base == CFG_FDOHM_BASE) {
+ return (*(volatile ushort *)fpga->conf_base) & 0xff;
+ }
+ else {
return *(volatile ulong *)fpga->conf_base;
+ }
case FPGA_INIT_PORTS:
immr->im_ioport.iop_ppard &= ~fpga->init_mask; /* INIT I/O */
}
return 0;
}
-
#include <ioports.h>
#include <mpc8260.h>
+#include "scm.h"
+
+static void config_scoh_cs(void);
+extern int fpga_init(void);
+
+#if 0
+#define DEBUGF(fmt,args...) printf (fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+
/*
* I/O Port configuration table
*
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
},
- /* Port C */
+ /* Port C configuration */
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK1 */
/* PC30 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK1 */
/* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */
/* PC15 */ { 0, 0, 0, 1, 0, 0 },
/* PC14 */ { 0, 1, 0, 0, 0, 0 },
- /* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* RES_PHY_L */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* RES_PHY_L */
/* PC12 */ { 0, 0, 0, 1, 0, 0 },
/* PC11 */ { 0, 0, 0, 1, 0, 0 },
/* PC10 */ { 0, 0, 0, 1, 0, 0 },
- /* PC9 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TSYNC */
- /* PC8 */ { 1, 0, 0, 0, 0, 0 }, /* FEP_RDY */
+ /* PC9 */ { 0, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TSYNC */
+ /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* FEP_RDY */
/* PC7 */ { 0, 0, 0, 0, 0, 0 },
- /* PC6 */ { 1, 0, 0, 0, 0, 0 }, /* UC4_ALARM_L */
- /* PC5 */ { 1, 0, 0, 0, 0, 0 }, /* UC3_ALARM_L */
- /* PC4 */ { 1, 0, 0, 0, 0, 0 }, /* UC2_ALARM_L */
- /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* RES_MISC_L */
- /* PC2 */ { 1, 0, 0, 1, 0, 0 }, /* RES_OH_L */
- /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* RES_DOHM_L */
- /* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* RES_FIOX_L */
+ /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* UC4_ALARM_L */
+ /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* UC3_ALARM_L */
+ /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* UC2_ALARM_L */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* RES_MISC_L */
+ /* PC2 */ { 0, 0, 0, 1, 0, 0 }, /* RES_OH_L */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* RES_DOHM_L */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* RES_FIOX_L */
},
- /* Port D */
+ /* Port D configuration */
{ /* conf ppar psor pdir podr pdat */
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* INIT_F */
+ /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_F */
/* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_F */
- /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* INIT_D */
+ /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_D */
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_D */
/* PD25 */ { 0, 0, 0, 1, 0, 0 },
/* PD24 */ { 0, 0, 0, 1, 0, 0 },
/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
/* PD7 */ { 0, 0, 0, 1, 0, 1 },
/* PD6 */ { 0, 0, 0, 1, 0, 1 },
- /* PD5 */ { 1, 0, 0, 1, 0, 1 }, /* PROG_F */
- /* PD4 */ { 1, 0, 0, 1, 0, 1 }, /* PROG_D */
+ /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_F */
+ /* PD4 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_D */
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
*/
int power_on_reset(void)
{
+ init_data_t *idata = (init_data_t *)(CFG_INIT_RAM_ADDR +
+ CFG_INIT_DATA_OFFSET);
/* Test Reset Status Register */
- return ((volatile immap_t *)CFG_IMMR)->im_clkrst.car_rsr & RSR_CSRS ? 0:1;
+ return idata->reset_status & RSR_CSRS ? 0:1;
}
long int initdram(int board_type)
icache_enable();
+ config_scoh_cs();
+
return (psize);
}
+/* ------------------------------------------------------------------------- */
-/*-----------------------------------------------------------------------
- * Process Hardware Information Block:
- *
- * If we boot on a system fresh from factory, check if the Hardware
- * Information Block exists and save the information it contains.
- *
- * The TQM8xxL / TQM82xx Hardware Information Block is defined as
- * follows:
- * - located in first flash bank
- * - starts at offset 0x0003FFC0
- * - size 0x00000040
- *
- * Internal structure:
- * - sequence of ASCII character strings
- * - fields separated by a single space character (0x20)
- * - last field terminated by NUL character (0x00)
- * - remaining space filled with NUL characters (0x00)
- *
- * Fields in Hardware Information Block:
- * 1) Module Type
- * 2) Serial Number
- * 3) First MAC Address
- * 4) Number of additional MAC addresses
- */
-
-void load_sernum_ethaddr (bd_t *bd)
+static void config_scoh_cs(void)
{
- unsigned char *hwi;
- unsigned char serial [CFG_HWINFO_SIZE];
- unsigned char ethaddr[CFG_HWINFO_SIZE];
- unsigned short ih, is, ie, part;
-
- hwi = (unsigned char *)(CFG_FLASH_BASE + CFG_HWINFO_OFFSET);
- ih = is = ie = 0;
-
- if (*((unsigned long *)hwi) != (unsigned long)CFG_HWINFO_MAGIC) {
- return;
- }
-
- part = 1;
-
- /* copy serial # / MAC address */
- while ((hwi[ih] != '\0') && (ih < CFG_HWINFO_SIZE)) {
- if (hwi[ih] < ' ' || hwi[ih] > '~') { /* ASCII strings! */
- return;
- }
- switch (part) {
- default: /* Copy serial # */
- if (hwi[ih] == ' ') {
- ++part;
- }
- serial[is++] = hwi[ih];
- break;
- case 3: /* Copy MAC address */
- if (hwi[ih] == ' ') {
- ++part;
- break;
- }
- ethaddr[ie++] = hwi[ih];
- if ((ie % 3) == 2)
- ethaddr[ie++] = ':';
- break;
- }
- ++ih;
- }
- serial[is] = '\0';
- if (ie && ethaddr[ie-1] == ':')
- --ie;
- ethaddr[ie] = '\0';
-
- /* set serial# and ethaddr if not yet defined */
- if (getenv("serial#") == NULL) {
- setenv ("serial#", serial);
- }
-
- if (getenv("ethaddr") == NULL) {
- setenv ("ethaddr", ethaddr);
- }
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile memctl8260_t *memctl = &immr->im_memctl;
+ volatile can_reg_t *can = (volatile can_reg_t *)CFG_CAN0_BASE;
+ volatile uint tmp, i;
+
+ /* Initialize OR3 / BR3 for CAN Bus Controller 0 */
+ memctl->memc_or3 = CFG_CAN0_OR3;
+ memctl->memc_br3 = CFG_CAN0_BR3;
+ /* Initialize OR4 / BR4 for CAN Bus Controller 1 */
+ memctl->memc_or4 = CFG_CAN1_OR4;
+ memctl->memc_br4 = CFG_CAN1_BR4;
+
+ /* Initialize MAMR to write in the array at address 0x0 */
+ memctl->memc_mamr = 0x00 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
+
+ /* Initialize UPMA for CAN: single read */
+ memctl->memc_mdr = 0xcffeec00;
+ udelay(1); /* Necessary to have the data correct in the UPM array!!!! */
+ /* The read on the CAN controller write the data of mdr in UPMA array. */
+ /* The index to the array will be incremented automatically
+ through this read */
+ tmp = can->cpu_interface;
+
+ memctl->memc_mdr = 0x0ffcec00;
+ udelay(1);
+ tmp = can->cpu_interface;
+
+ memctl->memc_mdr = 0x0ffcec00;
+ udelay(1);
+ tmp = can->cpu_interface;
+
+ memctl->memc_mdr = 0x0ffcec00;
+ udelay(1);
+ tmp = can->cpu_interface;
+
+ memctl->memc_mdr = 0x0ffcec00;
+ udelay(1);
+ tmp = can->cpu_interface;
+
+ memctl->memc_mdr = 0x0ffcfc00;
+ udelay(1);
+ tmp = can->cpu_interface;
+
+ memctl->memc_mdr = 0x0ffcfc00;
+ udelay(1);
+ tmp = can->cpu_interface;
+
+ memctl->memc_mdr = 0xfffdec07;
+ udelay(1);
+ tmp = can->cpu_interface;
+
+
+ /* Initialize MAMR to write in the array at address 0x18*/
+ memctl->memc_mamr = 0x18 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
+
+ /* Initialize UPMA for CAN: single write */
+ memctl->memc_mdr = 0xfcffec00;
+ udelay(1);
+ tmp = can->cpu_interface;
+
+ memctl->memc_mdr = 0x00ffec00;
+ udelay(1);
+ tmp = can->cpu_interface;
+
+ memctl->memc_mdr = 0x00ffec00;
+ udelay(1);
+ tmp = can->cpu_interface;
+
+ memctl->memc_mdr = 0x00ffec00;
+ udelay(1);
+ tmp = can->cpu_interface;
+
+ memctl->memc_mdr = 0x00ffec00;
+ udelay(1);
+ tmp = can->cpu_interface;
+
+ memctl->memc_mdr = 0x00fffc00;
+ udelay(1);
+ tmp = can->cpu_interface;
+
+ memctl->memc_mdr = 0x00fffc00;
+ udelay(1);
+ tmp = can->cpu_interface;
+
+ memctl->memc_mdr = 0x30ffec07;
+ udelay(1);
+ tmp = can->cpu_interface;
+
+ /* Initialize MAMR */
+ memctl->memc_mamr = MxMR_GPL_x4DIS; /* GPL_B4 ouput line Disable */
+
+
+ /* Initialize OR5 / BR5 for the extended EEPROM Bank0 */
+ memctl->memc_or5 = CFG_EXTPROM_OR5;
+ memctl->memc_br5 = CFG_EXTPROM_BR5;
+ /* Initialize OR6 / BR6 for the extended EEPROM Bank1 */
+ memctl->memc_or6 = CFG_EXTPROM_OR6;
+ memctl->memc_br6 = CFG_EXTPROM_BR6;
+
+ /* Initialize OR7 / BR7 for the Glue Logic */
+ memctl->memc_or7 = CFG_FIOX_OR7;
+ memctl->memc_br7 = CFG_FIOX_BR7;
+
+ /* Initialize OR8 / BR8 for the DOH Logic */
+ memctl->memc_or8 = CFG_FDOHM_OR8;
+ memctl->memc_br8 = CFG_FDOHM_BR8;
+
+ DEBUGF("OR0 %08x BR0 %08x\n", memctl->memc_or0, memctl->memc_br0);
+ DEBUGF("OR1 %08x BR1 %08x\n", memctl->memc_or1, memctl->memc_br1);
+ DEBUGF("OR2 %08x BR2 %08x\n", memctl->memc_or2, memctl->memc_br2);
+ DEBUGF("OR3 %08x BR3 %08x\n", memctl->memc_or3, memctl->memc_br3);
+ DEBUGF("OR4 %08x BR4 %08x\n", memctl->memc_or4, memctl->memc_br4);
+ DEBUGF("OR5 %08x BR5 %08x\n", memctl->memc_or5, memctl->memc_br5);
+ DEBUGF("OR6 %08x BR6 %08x\n", memctl->memc_or6, memctl->memc_br6);
+ DEBUGF("OR7 %08x BR7 %08x\n", memctl->memc_or7, memctl->memc_br7);
+ DEBUGF("OR8 %08x BR8 %08x\n", memctl->memc_or8, memctl->memc_br8);
+
+ DEBUGF("UPMA addr 0x0\n");
+ memctl->memc_mamr = 0x00 | MxMR_OP_RARR | MxMR_GPL_x4DIS;
+ for (i=0; i< 0x8; i++)
+ {
+ tmp = can->cpu_interface;
+ udelay(1);
+ DEBUGF(" %08x ", memctl->memc_mdr);
+ }
+ DEBUGF("\nUPMA addr 0x18\n");
+ memctl->memc_mamr = 0x18 | MxMR_OP_RARR | MxMR_GPL_x4DIS;
+ for (i=0; i< 0x8; i++)
+ {
+ tmp = can->cpu_interface;
+ udelay(1);
+ DEBUGF(" %08x ", memctl->memc_mdr);
+ }
+ DEBUGF("\n");
+ memctl->memc_mamr = MxMR_GPL_x4DIS;
}
/* ------------------------------------------------------------------------- */
void misc_init_r (bd_t *dummy)
{
- fpga_init();
+ fpga_init();
}
/* ------------------------------------------------------------------------- */
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SCM_H
+#define __SCM_H
+
+/*----------------*/
+/* CAN Structures */
+/*----------------*/
+
+/* Message */
+typedef struct can_msg {
+ uchar ctrl_0;
+ uchar ctrl_1;
+ uchar arbit_0;
+ uchar arbit_1;
+ uchar arbit_2;
+ uchar arbit_3;
+ uchar config;
+ uchar data[8];
+} can_msg_t;
+
+/* CAN Register */
+typedef struct can_reg {
+ uchar ctrl;
+ uchar status;
+ uchar cpu_interface;
+ uchar resv0;
+ ushort high_speed_rd;
+ ushort gbl_mask_std;
+ uint gbl_mask_extd;
+ uint msg15_mask;
+ can_msg_t msg1 __attribute__ ((packed));
+ uchar clkout;
+ can_msg_t msg2 __attribute__ ((packed));
+ uchar bus_config;
+ can_msg_t msg3 __attribute__ ((packed));
+ uchar bit_timing_0;
+ can_msg_t msg4 __attribute__ ((packed));
+ uchar bit_timing_1;
+ can_msg_t msg5 __attribute__ ((packed));
+ uchar interrupt;
+ can_msg_t msg6 __attribute__ ((packed));
+ uchar resv1;
+ can_msg_t msg7 __attribute__ ((packed));
+ uchar resv2;
+ can_msg_t msg8 __attribute__ ((packed));
+ uchar resv3;
+ can_msg_t msg9 __attribute__ ((packed));
+ uchar p1conf;
+ can_msg_t msg10 __attribute__ ((packed));
+ uchar p2conf;
+ can_msg_t msg11 __attribute__ ((packed));
+ uchar p1in;
+ can_msg_t msg12 __attribute__ ((packed));
+ uchar p2in;
+ can_msg_t msg13 __attribute__ ((packed));
+ uchar p1out;
+ can_msg_t msg14 __attribute__ ((packed));
+ uchar p2out;
+ can_msg_t msg15 __attribute__ ((packed));
+ uchar ser_res_addr;
+ uchar resv_cs[0x8000-0x100]; /* 0x8000 is the min size for CS */
+} can_reg_t;
+
+
+#endif /* __SCM_H */
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-fpga_t* fpga_get(char* fpga_name)
+
+static int fpga_get_version(fpga_t* fpga, char* name)
+{
+ char vname[12];
+ /*
+ * Net-list string format:
+ * "vvvvvvvvddddddddn...".
+ * Version Date Name
+ * "0000000322042002PUMA" = PUMA version 3 from 22.04.2002.
+ */
+ if (strlen(name) < (16 + strlen(fpga->name)))
+ goto failure;
+ /* Check FPGA name */
+ if (strcmp(&name[16], fpga->name) != 0)
+ goto failure;
+ /* Get version number */
+ memcpy(vname, name, 8);
+ vname[8] = '\0';
+ return simple_strtoul(vname, NULL, 16);
+
+ failure:
+ printf("Image name %s is invalid\n", name);
+ return -1;
+}
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+static fpga_t* fpga_get(char* fpga_name)
{
char name[FPGA_NAME_LEN];
int i;
#define FPGA_LOAD_TIMEOUT 100 /* = 10 ms */
-static int fpga_load (fpga_t* fpga, ulong addr)
+static int fpga_load (fpga_t* fpga, ulong addr, int checkall)
{
volatile uchar *fpga_addr = (volatile uchar *)fpga->conf_base;
image_header_t hdr;
ulong len, checksum;
uchar *data = (uchar *)&hdr;
char *s, msg[32];
- int verify, id, i;
+ int verify, i;
/*
* Check the image header and data of the net-list
}
}
- id = simple_strtoul (hdr.ih_name, NULL, 16);
-
+ if (checkall && fpga_get_version(fpga, hdr.ih_name) < 0)
+ return 1;
+
/* align length */
if (len & 1)
++len;
printf ("FPGA load %s: addr %08lx: ",
fpga->name, addr);
- fpga_load (fpga, addr);
+ fpga_load (fpga, addr, 1);
}
else if (strncmp(argv[1], "rese", 4) == 0) { /* reset */
}
hdr = (image_header_t *)addr;
- new_id = simple_strtoul(hdr->ih_name, NULL, 16);
+ if ((new_id = fpga_get_version(fpga, hdr->ih_name)) == -1)
+ return 1;
+
do_load = 1;
if (!power_on_reset() && fpga_control(fpga, FPGA_DONE_IS_HIGH)) {
if (do_load) {
printf ("loading ");
- fpga_load (fpga, addr);
+ fpga_load (fpga, addr, 0);
} else {
printf ("loaded (%08lx)\n", old_id);
}
env_relocate (reloc_off);
#if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \
- defined(CONFIG_CCM) || defined(CONFIG_SCM)
+ defined(CONFIG_CCM)
load_sernum_ethaddr(bd);
#endif
/* IP Address */
#define ATAPI_TIME_OUT 7000 /* 7 sec timeout (5 sec seems to work...) */
+#define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
static void __inline__ outb(int dev, int port, unsigned char val);
static unsigned char __inline__ inb(int dev, int port);
} while (c & ATA_STAT_BUSY);
if (c & (ATA_STAT_BUSY | ATA_STAT_FAULT)) {
- printf ("Status 0x%02x ", c);
+ puts ("not available ");
+ PRINTF ("Status = 0x%02X ", c);
#ifndef CONFIG_ATAPI /* ATAPI Devices do not set DRDY */
} else if ((c & ATA_STAT_READY) == 0) {
puts ("not available ");
c = ide_wait (device, IDE_TIME_OUT);
}
ide_led (DEVICE_LED(device), 0); /* LED off */
-
- if (((c & ATA_STAT_READY) == 0) ||
+
+ if (((c & ATA_STAT_DRQ) == 0) ||
((c & (ATA_STAT_FAULT|ATA_STAT_ERR)) != 0) ) {
dev_desc->type=DEV_TYPE_UNKNOWN;
return;
dev_desc->blksz=ATA_BLOCKSIZE;
dev_desc->lun=0; /* just to fill something in... */
+#if 0 /* only used to test the powersaving mode,
+ * if enabled, the drive goes after 5 sec
+ * in standby mode */
+ outb (device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+ c = ide_wait (device, IDE_TIME_OUT);
+ outb (device, ATA_SECT_CNT, 1);
+ outb (device, ATA_LBA_LOW, 0);
+ outb (device, ATA_LBA_MID, 0);
+ outb (device, ATA_LBA_HIGH, 0);
+ outb (device, ATA_DEV_HD, ATA_LBA |
+ ATA_DEVICE(device));
+ outb (device, ATA_COMMAND, 0xe3);
+ udelay (50);
+ c = ide_wait (device, IDE_TIME_OUT); /* can't take over 500 ms */
+#endif
}
{
ulong n = 0;
unsigned char c;
+ unsigned char pwrsave=0; /* power save */
PRINTF ("ide_read dev %d start %lX, blocks %lX buffer at %lX\n",
device, blknr, blkcnt, (ulong)buffer);
/* Select device
*/
outb (device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+ c = ide_wait (device, IDE_TIME_OUT);
+
+ if (c & ATA_STAT_BUSY) {
+ printf ("IDE read: device %d not ready\n", device);
+ goto IDE_READ_E;
+ }
+
+ /* first check if the drive is in Powersaving mode, if yes,
+ * increase the timeout value */
+ outb (device, ATA_COMMAND, ATA_CMD_CHK_PWR);
+ udelay (50);
+
+ c = ide_wait (device, IDE_TIME_OUT); /* can't take over 500 ms */
+
+ if (c & ATA_STAT_BUSY) {
+ printf ("IDE read: device %d not ready\n", device);
+ goto IDE_READ_E;
+ }
+ if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
+ printf ("No Powersaving mode %X\n", c);
+ }
+ else {
+ c = inb(device,ATA_SECT_CNT);
+ PRINTF("Powersaving %02X\n",c);
+ if(c==0)
+ pwrsave=1;
+ }
+
while (blkcnt-- > 0) {
udelay (50);
- c = ide_wait (device, IDE_TIME_OUT); /* can't take over 500 ms */
+ if(pwrsave) {
+ c = ide_wait (device, IDE_SPIN_UP_TIME_OUT); /* may take up to 4 sec */
+ pwrsave=0;
+ }
+ else
+ c = ide_wait (device, IDE_TIME_OUT); /* can't take over 500 ms */
if ((c&(ATA_STAT_DRQ|ATA_STAT_BUSY|ATA_STAT_ERR)) != ATA_STAT_DRQ) {
printf ("Error (no IRQ) dev %d blk %ld: status 0x%02x\n",
++blknr;
buffer += ATA_SECTORWORDS;
}
-
+IDE_READ_E:
ide_led (DEVICE_LED(device), 0); /* LED off */
return (n);
}
while (blkcnt-- > 0) {
c = ide_wait (device, IDE_TIME_OUT);
-
+
if (c & ATA_STAT_BUSY) {
printf ("IDE read: device %d not ready\n", device);
goto WR_OUT;
#define AT_PRINTF(fmt,args...)
#endif
+/* since ATAPI may use commands with not 4 bytes alligned length
+ * we have our own transfer functions, 2 bytes alligned */
+static void
+output_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+ ushort *dbuf;
+ volatile ushort *pbuf;
+
+ pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG);
+ dbuf = (ushort *)sect_buf;
+ while (shorts--) {
+ __asm__ volatile ("eieio");
+ *pbuf = *dbuf++;
+ }
+}
+
+static void
+input_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+ ushort *dbuf;
+ volatile ushort *pbuf;
+
+ pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG);
+ dbuf = (ushort *)sect_buf;
+ while (shorts--) {
+ __asm__ volatile ("eieio");
+ *dbuf++ = *pbuf;
+ }
+}
+
+/*
+ * Wait until (Status & mask) == res, or timeout (in ms)
+ * Return last status
+ * This is used since some ATAPI CD ROMs clears their Busy Bit first
+ * and then they set their DRQ Bit
+ */
+static uchar atapi_wait_mask (int dev, ulong t,uchar mask, uchar res)
+{
+ ulong delay = 10 * t; /* poll every 100 us */
+ uchar c;
+
+ c = inb(dev,ATA_DEV_CTL); /* prevents to read the status before valid */
+ while (((c = inb(dev, ATA_STATUS)) & mask)
+ != res) {
+ /* break if error occurs (doesn't make sense to wait more) */
+ if((c & ATA_STAT_ERR)==ATA_STAT_ERR)
+ break;
+ udelay (100);
+ if (delay-- == 0) {
+ break;
+ }
+ }
+ return (c);
+}
+
/*
* issue an atapi command
*/
unsigned char atapi_issue(int device,unsigned char* ccb,int ccblen, unsigned char * buffer,int buflen)
{
- unsigned char c,err;
- int n;
+ unsigned char c,err,mask,res;
+ int n;
ide_led (DEVICE_LED(device), 1); /* LED on */
/* Select device
*/
+ mask = ATA_STAT_BUSY|ATA_STAT_DRQ;
+ res = 0;
outb (device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
- c = ide_wait (device, ATAPI_TIME_OUT);
-
- if (c & ATA_STAT_BUSY) {
- printf ("ATAPI_ISSUE: device %d not ready\n", device);
+ c = atapi_wait_mask(device,ATAPI_TIME_OUT,mask,res);
+ if ((c & mask) != res) {
+ printf ("ATAPI_ISSUE: device %d not ready status %X\n", device,c);
err=0xFF;
goto AI_OUT;
}
+ /* write taskfile */
outb (device, ATA_ERROR_REG, 0); /* no DMA, no overlaped */
outb (device, ATA_CYL_LOW, (unsigned char)(buflen & 0xFF));
outb (device, ATA_CYL_HIGH, (unsigned char)((buflen<<8) & 0xFF));
outb (device, ATA_COMMAND, ATAPI_CMD_PACKET);
udelay (50);
- c = ide_wait (device, ATAPI_TIME_OUT); /* can't take over 500 ms */
+
+ mask = ATA_STAT_DRQ|ATA_STAT_BUSY|ATA_STAT_ERR;
+ res = ATA_STAT_DRQ;
+ c = atapi_wait_mask(device,ATAPI_TIME_OUT,mask,res);
- if ((c&(ATA_STAT_DRQ|ATA_STAT_BUSY|ATA_STAT_ERR)) != ATA_STAT_DRQ) { /* DRQ must be 1, BSY 0 */
- printf ("ATTAPI_ISSUE: Error (no IRQ) before sending ccb dev %d status 0x%02x\n",device,c);
+ if ((c & mask) != res) { /* DRQ must be 1, BSY 0 */
+ printf ("ATTAPI_ISSUE: Error (no IRQ) before sending ccb dev %d status 0x%02x\n",device,c);
err=0xFF;
goto AI_OUT;
}
- output_data (device, (unsigned long *)ccb,ccblen/2); /* write command block */
- /*while ((inb(device,ATA_STATUS) & ATA_STAT_BUSY)==0) */
-
- udelay (50); /* device must set bsy */
- /*c = inb (device, ATA_STATUS);*/ /* clear IRQ */
-
- c = ide_wait (device, ATAPI_TIME_OUT); /* wait until BSY=0, DRQ=1 */
-
- if ((c&(ATA_STAT_DRQ|ATA_STAT_BUSY|ATA_STAT_ERR)) != ATA_STAT_DRQ) {
- if ((c&ATA_STAT_ERR) == ATA_STAT_ERR) {
- err=(inb(device,ATA_ERROR_REG));
- AT_PRINTF("atapi_issue returned sense key %X\n",err);
+ output_data_shorts (device, (unsigned short *)ccb,ccblen/2); /* write command block */
+ /* ATAPI Command written wait for completition */
+ udelay (5000); /* device must set bsy */
+
+ mask = ATA_STAT_DRQ|ATA_STAT_BUSY|ATA_STAT_ERR;
+ /* if no data wait for DRQ = 0 BSY = 0
+ * if data wait for DRQ = 1 BSY = 0 */
+ res=0;
+ if(buflen)
+ res = ATA_STAT_DRQ;
+ c = atapi_wait_mask(device,ATAPI_TIME_OUT,mask,res);
+ if ((c & mask) != res ) {
+ if (c & ATA_STAT_ERR) {
+ err=(inb(device,ATA_ERROR_REG))>>4;
+ AT_PRINTF("atapi_issue 1 returned sense key %X status %02X\n",err,c);
} else {
- /* maybe no data command ? */
- if (buflen==0) {
- err=0;
- } else {
- printf ("ATTAPI_ISSUE: (no IRQ) after sending ccb (%x) status 0x%02x\n", ccb[0],c);
- err=0xFF;
- }
+ printf ("ATTAPI_ISSUE: (no DRQ) after sending ccb (%x) status 0x%02x\n", ccb[0],c);
+ err=0xFF;
}
goto AI_OUT;
}
n=inb(device, ATA_CYL_HIGH);
n<<=8;
n+=inb(device, ATA_CYL_LOW);
- AT_PRINTF("ATAPI_ISSUE: %d Bytes to transfer\n",n);
-
- /* ok now decide if it is an in or output */
- if ((inb(device, ATA_SECT_CNT)&0x02)==0) {
- AT_PRINTF("Write to device\n");
- output_data(device,(unsigned long *)buffer,n>>2);
- } else {
- AT_PRINTF("Read from device @ %p words %d\n",buffer,n>>2);
- input_data(device,(unsigned long *)buffer,n>>2);
+ if(n>buflen) {
+ printf("ERROR, transfer bytes %d requested only %d\n",n,buflen);
+ err=0xff;
+ goto AI_OUT;
}
-
- c = inb (device, ATA_STATUS); /* clear IRQ */
+ if((n==0)&&(buflen<0)) {
+ printf("ERROR, transfer bytes %d requested %d\n",n,buflen);
+ err=0xff;
+ goto AI_OUT;
+ }
+ if(n!=buflen) {
+ AT_PRINTF("WARNING, transfer bytes %d not equal with requested %d\n",n,buflen);
+ }
+ if(n!=0) { /* data transfer */
+ AT_PRINTF("ATAPI_ISSUE: %d Bytes to transfer\n",n);
+ /* we transfer shorts */
+ n>>=1;
+ /* ok now decide if it is an in or output */
+ if ((inb(device, ATA_SECT_CNT)&0x02)==0) {
+ AT_PRINTF("Write to device\n");
+ output_data_shorts(device,(unsigned short *)buffer,n);
+ } else {
+ AT_PRINTF("Read from device @ %p shorts %d\n",buffer,n);
+ input_data_shorts(device,(unsigned short *)buffer,n);
+ }
+ }
+ udelay(5000); /* seems that some CD ROMs need this... */
+ mask = ATA_STAT_BUSY|ATA_STAT_ERR;
+ res=0;
+ c = atapi_wait_mask(device,ATAPI_TIME_OUT,mask,res);
if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
- err=(inb(device,ATA_ERROR_REG) >> 8) &0x0F;
- AT_PRINTF("atapi_issue returned sense key %X\n",err);
+ err=(inb(device,ATA_ERROR_REG) >> 4);
+ AT_PRINTF("atapi_issue 2 returned sense key %X status %X\n",err,c);
} else {
err = 0;
}
* sending the command to atapi_issue. If an status other than good
* returns, an request_sense will be issued
*/
+
+#define ATAPI_DRIVE_NOT_READY 100
+#define ATAPI_UNIT_ATTN 10
+
unsigned char atapi_issue_autoreq (int device,
unsigned char* ccb,
int ccblen,
unsigned char *buffer,
int buflen)
{
- unsigned char sense_data[16],sense_ccb[12];
- unsigned char res;
- int i,retrycnt;
+ unsigned char sense_data[18],sense_ccb[12];
+ unsigned char res,key,asc,ascq;
+ int notready,unitattn;
+
+ unitattn=ATAPI_UNIT_ATTN;
+ notready=ATAPI_DRIVE_NOT_READY;
- retrycnt=0;
retry:
res= atapi_issue(device,ccb,ccblen,buffer,buflen);
if (res==0)
AT_PRINTF("(auto_req)atapi_issue returned sense key %X\n",res);
- for (i=0;i<12;i++)
- sense_ccb[i]=0; /* initialize it to zero */
-
+ memset(sense_ccb,0,sizeof(sense_ccb));
+ memset(sense_data,0,sizeof(sense_data));
sense_ccb[0]=ATAPI_CMD_REQ_SENSE;
- sense_ccb[4]=16; /* allocation Legnth */
-
- res=atapi_issue(device,sense_ccb,12,sense_data,14);
+ sense_ccb[4]=18; /* allocation Legnth */
+ res=atapi_issue(device,sense_ccb,12,sense_data,18);
+ key=(sense_data[2]&0xF);
+ asc=(sense_data[12]);
+ ascq=(sense_data[13]);
+
AT_PRINTF("ATAPI_CMD_REQ_SENSE returned %x\n",res);
AT_PRINTF(" Sense page: %02X key %02X ASC %02X ASCQ %02X\n",
sense_data[0],
- sense_data[2]&0xF,
- sense_data[12],
- sense_data[13]);
-
- if (((sense_data[2]&0xF)==0) && (sense_data[12]==0) && (sense_data[13]==0))
- return (0); /* ok device ready */
+ key,
+ asc,
+ ascq);
- if (((sense_data[2]&0xF)==0x02) && (sense_data[12]==0x04) && (sense_data[13]!=0x01)) {
- printf("Error\n");
- return (0xFF);
- }
+ if((key==0))
+ return 0; /* ok device ready */
- if (((sense_data[2]&0xF)==0x02) && (sense_data[12]==0x3A)) {
- AT_PRINTF("Media not present\n");
- return (0xFF);
+ if((key==6)|| (asc==0x29) || (asc==0x28)) { /* Unit Attention */
+ if(unitattn-->0) {
+ udelay(200*1000);
+ goto retry;
+ }
+ printf("Unit Attention, tried %d\n",ATAPI_UNIT_ATTN);
+ goto error;
}
-
- if ((sense_data[2]&0xF)==0x06) {
- AT_PRINTF("Unit attention...retry\n");
- if (retrycnt++<4)
+ if((asc==0x4) && (ascq==0x1)) { /* not ready, but will be ready soon */
+ if (notready-->0) {
+ udelay(200*1000);
goto retry;
- return (0xFF);
+ }
+ printf("Drive not ready, tried %d times\n",ATAPI_DRIVE_NOT_READY);
+ goto error;
}
-
- printf ("unknown sense_key\n");
+ if(asc==0x3a) {
+ AT_PRINTF("Media not present\n");
+ goto error;
+ }
+ printf ("ERROR: Unknown Sense key %02X ASC %02X ASCQ %02X\n",key,asc,ascq);
+error:
+ AT_PRINTF ("ERROR Sense key %02X ASC %02X ASCQ %02X\n",key,asc,ascq);
return (0xFF);
}
-
+
static void atapi_inquiry(block_dev_desc_t * dev_desc)
{
unsigned char ccb[12]; /* Command descriptor block */
unsigned char iobuf[64]; /* temp buf */
unsigned char c;
- int i,device;
+ int device;
device=dev_desc->dev;
dev_desc->type=DEV_TYPE_UNKNOWN; /* not yet valid */
dev_desc->block_read=atapi_read;
- for (i=0;i<12;i++)
- ccb[i]=0; /* initialize it to zero */
+ memset(ccb,0,sizeof(ccb));
+ memset(iobuf,0,sizeof(iobuf));
ccb[0]=ATAPI_CMD_INQUIRY;
ccb[4]=40; /* allocation Legnth */
else
dev_desc->removable = 0;
- for (i=0;i<12;i++)
- ccb[i]=0; /* initialize it to zero */
-
+ memset(ccb,0,sizeof(ccb));
+ memset(iobuf,0,sizeof(iobuf));
ccb[0]=ATAPI_CMD_START_STOP;
- ccb[4]=0x01; /* start */
+ ccb[4]=0x03; /* start */
c=atapi_issue_autoreq(device,ccb,12,(unsigned char *)iobuf,0);
if (c!=0)
return;
- for (i=0;i<12;i++)
- ccb[i]=0; /* initialize it to zero */
+ memset(ccb,0,sizeof(ccb));
+ memset(iobuf,0,sizeof(iobuf));
+ c=atapi_issue_autoreq(device,ccb,12,(unsigned char *)iobuf,0);
+
+ AT_PRINTF("ATAPI_CMD_UNIT_TEST_READY returned %x\n",c);
+ if (c!=0)
+ return;
+ memset(ccb,0,sizeof(ccb));
+ memset(iobuf,0,sizeof(iobuf));
ccb[0]=ATAPI_CMD_READ_CAP;
c=atapi_issue_autoreq(device,ccb,12,(unsigned char *)iobuf,8);
AT_PRINTF("ATAPI_CMD_READ_CAP returned %x\n",c);
* we transfer only one block per command, since the multiple DRQ per
* command is not yet implemented
*/
-#define ATAPI_READ_MAX_BYTES 2048 /* we read max 32kbytes */
+#define ATAPI_READ_MAX_BYTES 2048 /* we read max 2kbytes */
#define ATAPI_READ_BLOCK_SIZE 2048 /* assuming CD part */
#define ATAPI_READ_MAX_BLOCK ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE /* max blocks */
# define LCD_INFO_Y (VIDEO_FONT_HEIGHT)
#endif
-/************************************************************************/
-/* ** CONSOLE CONSTANTS */
-/************************************************************************/
-
-#if LCD_BPP == LCD_MONOCHROME
-
-/*
- * Simple color definitions
- */
-#define CONSOLE_COLOR_BLACK 0
-#define CONSOLE_COLOR_WHITE 1 /* Must remain last / highest */
-
-#else
-
-/*
- * Simple color definitions
- */
-#define CONSOLE_COLOR_BLACK 0
-#define CONSOLE_COLOR_RED 1
-#define CONSOLE_COLOR_GREEN 2
-#define CONSOLE_COLOR_YELLOW 3
-#define CONSOLE_COLOR_BLUE 4
-#define CONSOLE_COLOR_MAGENTA 5
-#define CONSOLE_COLOR_CYAN 6
-#define CONSOLE_COLOR_GREY 14
-#define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */
-
-#endif
-
-#if defined(CONFIG_LCD_LOGO) && (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET)
-#error Default Color Map overlaps with Logo Color Map
-#endif
-
-/************************************************************************/
-
-#ifndef PAGE_SIZE
-#define PAGE_SIZE 4096
-#endif
-
-/************************************************************************/
-
-ulong lcd_setmem (ulong addr);
-
-static void lcd_drawchars (ushort x, ushort y, uchar *str, int count);
-static inline void lcd_puts_xy (ushort x, ushort y, uchar *s);
-static inline void lcd_putc_xy (ushort x, ushort y, uchar c);
-
-static int lcd_init (bd_t *bd, void *lcdbase);
-static void lcd_ctrl_init (void *lcdbase);
-static void lcd_enable (void);
-static void *lcd_logo (bd_t *bd);
-static void lcd_setcolreg (ushort regno,
- ushort red, ushort green, ushort blue);
-static void lcd_initcolregs (void);
-static int lcd_getbgcolor (void);
-static void lcd_setfgcolor (int color);
-static void lcd_setbgcolor (int color);
-
-#ifdef NOT_USED_SO_FAR
-static void lcd_disable (void);
-static void lcd_getcolreg (ushort regno,
- ushort *red, ushort *green, ushort *blue);
-static int lcd_getfgcolor (void);
-#endif /* NOT_USED_SO_FAR */
-
/************************************************************************/
/************************************************************************/
static void *lcd_console_address; /* Start of console buffer */
+/************************************************************************/
+/* ** CONSOLE CONSTANTS */
+/************************************************************************/
+
+#if LCD_BPP == LCD_MONOCHROME
+
+/*
+ * Simple color definitions
+ */
+#define CONSOLE_COLOR_BLACK 0
+#define CONSOLE_COLOR_WHITE 1 /* Must remain last / highest */
+
+#else
+
+/*
+ * Simple color definitions
+ */
+#define CONSOLE_COLOR_BLACK 0
+#define CONSOLE_COLOR_RED 1
+#define CONSOLE_COLOR_GREEN 2
+#define CONSOLE_COLOR_YELLOW 3
+#define CONSOLE_COLOR_BLUE 4
+#define CONSOLE_COLOR_MAGENTA 5
+#define CONSOLE_COLOR_CYAN 6
+#define CONSOLE_COLOR_GREY 14
+#define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */
+
+#endif
+
+#if defined(CONFIG_LCD_LOGO) && (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET)
+#error Default Color Map overlaps with Logo Color Map
+#endif
+
+/************************************************************************/
+
+#ifndef PAGE_SIZE
+#define PAGE_SIZE 4096
+#endif
+
/************************************************************************/
/* ** CONSOLE DEFINITIONS & FUNCTIONS */
static short console_col;
static short console_row;
+/************************************************************************/
+
+ulong lcd_setmem (ulong addr);
+
+static void lcd_drawchars (ushort x, ushort y, uchar *str, int count);
+static inline void lcd_puts_xy (ushort x, ushort y, uchar *s);
+static inline void lcd_putc_xy (ushort x, ushort y, uchar c);
+
+static int lcd_init (bd_t *bd, void *lcdbase);
+static void lcd_ctrl_init (void *lcdbase);
+static void lcd_enable (void);
+static void *lcd_logo (bd_t *bd);
+#if LCD_BPP == LCD_COLOR8
+static void lcd_setcolreg (ushort regno,
+ ushort red, ushort green, ushort blue);
+#endif
+#if LCD_BPP == LCD_MONOCHROME
+static void lcd_initcolregs (void);
+#endif
+static int lcd_getbgcolor (void);
+static void lcd_setfgcolor (int color);
+static void lcd_setbgcolor (int color);
+
+#ifdef NOT_USED_SO_FAR
+static void lcd_disable (void);
+static void lcd_getcolreg (ushort regno,
+ ushort *red, ushort *green, ushort *blue);
+static int lcd_getfgcolor (void);
+#endif /* NOT_USED_SO_FAR */
+
+/************************************************************************/
+
/*----------------------------------------------------------------------*/
static void console_scrollup (void)
/*----------------------------------------------------------------------*/
+#if LCD_BPP == LCD_COLOR8
static void
lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
{
red, green, blue,
cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]);
}
+#endif /* LCD_COLOR8 */
/*----------------------------------------------------------------------*/
+#if LCD_BPP == LCD_MONOCHROME
static
void lcd_initcolregs (void)
{
cp->lcd_cmap[(regno * 2) + 1] = regno & 0x0f;
}
}
+#endif
/*----------------------------------------------------------------------*/
static void *lcd_logo (bd_t *bd)
{
+#ifdef LCD_INFO
char info[80];
char temp[32];
+#endif /* LCD_INFO */
+
#ifdef CONFIG_LCD_LOGO
bitmap_plot (0, 0);
#endif /* CONFIG_LCD_LOGO */
return (-1);
if(ppr->desctype!=0x01) {
if(verb)
- printf(" first descriptor is NOT a primary desc\n");
+ printf ("** First descriptor is NOT a primary desc on %d:%d **\n",
+ dev_desc->dev, part_num);
return (-1);
}
if(strncmp(ppr->stand_ident,"CD001",5)!=0) {
if(verb)
- printf("ISO Ident: %s wrong\n",ppr->stand_ident);
+ printf ("** Wrong ISO Ident: %s on %d:%d **\n",
+ ppr->stand_ident,dev_desc->dev, part_num);
return (-1);
}
lastsect= ((ppr->firstsek_LEpathtab1_LE & 0x000000ff)<<24) +
break; /* boot entry found */
if(ppr->desctype==0xff) {
if(verb)
- printf(" No valid boot catalog found\n");
+ printf ("** No valid boot catalog found on %d:%d **\n",
+ dev_desc->dev, part_num);
return (-1);
}
}
/* boot entry found */
if(strncmp(pbr->ident_str,"EL TORITO SPECIFICATION",23)!=0) {
if(verb)
- printf("Ident: %s wrong\n",pbr->ident_str);
+ printf ("** Wrong El Torito ident: %s on %d:%d **\n",
+ pbr->ident_str,dev_desc->dev, part_num);
return (-1);
}
bootaddr=le32_to_int(pbr->pointer);
PRINTF(" Boot Entry at: %08lX\n",bootaddr);
- if (dev_desc->block_read (dev_desc->dev, bootaddr, 1, (ulong *) tmpbuf) != 1)
+ if (dev_desc->block_read (dev_desc->dev, bootaddr, 1, (ulong *) tmpbuf) != 1) {
+ if(verb)
+ printf ("** Can't read Boot Entry at %lX on %d:%d **\n",
+ bootaddr,dev_desc->dev, part_num);
return (-1);
+ }
chksum=0;
chksumbuf = (unsigned short *)tmpbuf;
for(i=0;i<0x10;i++)
chksum+=((chksumbuf[i] &0xff)<<8)+((chksumbuf[i] &0xff00)>>8);
if(chksum!=0) {
if(verb)
- printf(" checksum Error in booting catalog validation entry\n");
+ printf ("** Checksum Error in booting catalog validation entry on %d:%d **\n",
+ dev_desc->dev, part_num);
return (-1);
}
if((pve->key[0]!=0x55)||(pve->key[1]!=0xAA)) {
if(verb)
- printf(" key 0x55 0xAA error\n");
+ printf ("** Key 0x55 0xAA error on %d:%d **\n",
+ dev_desc->dev, part_num);
return(-1);
}
#ifdef CHECK_FOR_POWERPC_PLATTFORM
if(pve->platform!=0x01) {
if(verb)
- printf(" no PowerPC platform\n");
+ printf ("** No PowerPC platform CD on %d:%d **\n",
+ dev_desc->dev, part_num);
return(-1);
}
#endif
/* the validation entry seems to be ok, now search the "partition" */
entry_num=0;
offset=0x20;
- sprintf(info->name,"%.32s",pve->manu_str);
sprintf (info->type, "PPCBoot");
+ switch(dev_desc->if_type) {
+ case IF_TYPE_IDE:
+ case IF_TYPE_ATAPI:
+ sprintf (info->name, "hd%c%d\n", 'a' + dev_desc->dev, part_num);
+ break;
+ case IF_TYPE_SCSI:
+ sprintf (info->name, "sd%c%d\n", 'a' + dev_desc->dev, part_num);
+ break;
+ case IF_TYPE_USB:
+ sprintf (info->name, "usbd%c%d\n", 'a' + dev_desc->dev, part_num);
+ break;
+ case IF_TYPE_DOC:
+ sprintf (info->name, "docd%c%d\n", 'a' + dev_desc->dev, part_num);
+ break;
+ default:
+ sprintf (info->name, "xx%c%d\n", 'a' + dev_desc->dev, part_num);
+ break;
+ }
/* the bootcatalog (including validation Entry) is limited to 2048Bytes
* (63 boot entries + validation entry) */
while(offset<2048) {
}
else {
if(verb)
- printf(" part %d not found\n",part_num);
+ printf ("** Partition %d not found on device %d **\n",
+ part_num,dev_desc->dev);
return(-1);
}
}
/* if we reach this point entire sector has been
* searched w/o succsess */
if(verb)
- printf(" part %d not found\n",part_num);
+ printf ("** Partition %d not found on device %d **\n",
+ part_num,dev_desc->dev);
return(-1);
found:
if(pide->boot_ind!=0x88) {
if(verb)
- printf(" part %d is not bootable\n",part_num);
+ printf ("** Partition %d is not bootable on device %d **\n",
+ part_num,dev_desc->dev);
return (-1);
}
switch(pide->boot_media) {
}
newblkaddr=le32_to_int(pide->rel_block_addr);
info->start=newblkaddr;
- if(verb)
- printf(" part %d found @ %lx size %lx\n",part_num,newblkaddr,info->size);
+ PRINTF(" part %d found @ %lx size %lx\n",part_num,newblkaddr,info->size);
return 0;
}
int get_partition_info_iso(block_dev_desc_t * dev_desc, int part_num, disk_partition_t * info)
{
- return(get_partition_info_iso_verb(dev_desc, part_num, info, 0));
+ return(get_partition_info_iso_verb(dev_desc, part_num, info, 1));
}
#define ATA_CMD_WR_DMAN 0xCB /* Write DMA ( no retires) */
#define ATA_CMD_IDENT 0xEC /* Identify Device */
#define ATA_CMD_SETF 0xEF /* Set Features */
+#define ATA_CMD_CHK_PWR 0xE5 /* Check Power Mode */
/*
* ATAPI Commands
(CONFIG_CMD_DFL | \
CFG_CMD_IDE | \
CFG_CMD_DHCP | \
+ CFG_CMD_CACHE | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
+ CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_REGINFO | \
/************************************************************
* Ident
************************************************************/
-#define VERSION_TAG "dp_00006"
+#define VERSION_TAG "1.2.0"
#define CONFIG_IDENT_STRING "\n(c) 2001 by MPL AG Switzerland, MEV-10072-001 " VERSION_TAG
CFG_CMD_IDE | \
CFG_CMD_DHCP | \
CFG_CMD_PCI | \
+ CFG_CMD_CACHE | \
CFG_CMD_IRQ | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
/************************************************************
* Ident
************************************************************/
-#define VERSION_TAG "dp_00006"
+#define VERSION_TAG "1.2.0"
#define CONFIG_IDENT_STRING "\n(c) 2001 by MPL AG Switzerland, MEV-10066-001 " VERSION_TAG
#ifndef __CONFIG_H
#define __CONFIG_H
-/*
- * Imported from global configuration:
- * CONFIG_L2_CACHE
- * CONFIG_266MHz
- * CONFIG_300MHz
- */
-
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
-
+#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */
#define CONFIG_SCM 1 /* ...on a System Controller Module */
+#if (CONFIG_TQM8260 <= 100)
+# error "TQM8260 module revison not supported"
+#endif
+
+/* We use a TQM8260 module with a 300MHz CPU */
+#define CONFIG_300MHz
+
/* Define 60x busmode only if your TQM8260 has L2 cache! */
#ifdef CONFIG_L2_CACHE
# define CONFIG_BUSMODE_60x 1 /* bus mode: 60x */
* Software (bit-bang) I2C driver configuration
*/
-/* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */
-#if (CONFIG_TQM8260 <= 100)
-
-#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00020000)
-#define I2C_TRISTATE (iop->pdir &= ~0x00020000)
-#define I2C_READ ((iop->pdat & 0x00020000) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00020000; \
- else iop->pdat &= ~0x00020000
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00010000; \
- else iop->pdat &= ~0x00010000
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-#else
-
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
else iop->pdat &= ~0x00020000
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#endif
#define CFG_I2C_EEPROM_ADDR 0x50
#define CFG_I2C_EEPROM_ADDR_LEN 2
#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
#define CONFIG_BAUDRATE 230400
#else
-#define CONFIG_BAUDRATE 19200
+#define CONFIG_BAUDRATE 115200
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */
+#define CONFIG_MISC_INIT_R /* have misc_init_r() function */
+
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
/* CS3 - CAN 0
*/
-#define CFG_CAN0_BR3 ((CFG_CAN0_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
+#define CFG_CAN0_BR3 ((CFG_CAN0_BASE & BRx_BA_MSK) |\
+ BRx_PS_8 |\
+ BRx_MS_UPMA |\
+ BRx_V)
+
+#define CFG_CAN0_OR3 (P2SZ_TO_AM(CFG_CAN_SIZE) |\
+ ORxU_BI |\
+ ORxU_EHTR_4IDLE)
-#define CFG_CAN0_OR3 (P2SZ_TO_AM(CFG_CAN_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV4 |\
- ORxG_SETA | /* Ext. access termination */\
- ORxG_TRLX)
/* CS4 - CAN 1
*/
-#define CFG_CAN1_BR4 ((CFG_CAN1_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
+#define CFG_CAN1_BR4 ((CFG_CAN1_BASE & BRx_BA_MSK) |\
+ BRx_PS_8 |\
+ BRx_MS_UPMA |\
+ BRx_V)
-#define CFG_CAN1_OR4 (P2SZ_TO_AM(CFG_CAN_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV4 |\
- ORxG_SETA | /* Ext. access termination */\
- ORxG_TRLX)
+#define CFG_CAN1_OR4 (P2SZ_TO_AM(CFG_CAN_SIZE) |\
+ ORxU_BI |\
+ ORxU_EHTR_4IDLE)
/* CS5 - Extended PROM (16MB optional)
*/
#define CFG_EXTPROM_BR5 ((CFG_EXTPROM_BASE & BRx_BA_MSK)|\
- BRx_PS_32 |\
- BRx_MS_GPCM_P |\
- BRx_V)
+ BRx_PS_32 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
#define CFG_EXTPROM_OR5 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\
- ORxG_CSNT |\
- ORxG_ACS_DIV4 |\
- ORxG_SCY_5_CLK | /* Wait time: 2*SCY */\
- ORxG_TRLX)
+ ORxG_CSNT |\
+ ORxG_ACS_DIV4 |\
+ ORxG_SCY_5_CLK |\
+ ORxG_TRLX)
/* CS6 - Extended PROM (16MB optional)
*/
-#define CFG_EXTPROM_BR6 (((CFG_EXTPROM_BASE + \
- CFG_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\
- BRx_PS_32 |\
- BRx_MS_GPCM_P |\
- BRx_V)
+#define CFG_EXTPROM_BR6 (((CFG_EXTPROM_BASE + \
+ CFG_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\
+ BRx_PS_32 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
#define CFG_EXTPROM_OR6 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\
- ORxG_CSNT |\
- ORxG_ACS_DIV4 |\
- ORxG_SCY_5_CLK | /* Wait time: 2*SCY */\
- ORxG_TRLX)
+ ORxG_CSNT |\
+ ORxG_ACS_DIV4 |\
+ ORxG_SCY_5_CLK |\
+ ORxG_TRLX)
-/* CS7 - FIOX: Glue Logic
+/* CS7 - FPGA FIOX: Glue Logic
*/
-#define CFG_FIOX_BR7 ((CFG_FIOX_BASE & BRx_BA_MSK) |\
- BRx_PS_32 |\
- BRx_MS_GPCM_P |\
- BRx_V)
+#define CFG_FIOX_BR7 ((CFG_FIOX_BASE & BRx_BA_MSK) |\
+ BRx_PS_32 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
-#define CFG_FIOX_OR7 (P2SZ_TO_AM(CFG_FIOX_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV4 |\
- ORxG_SCY_5_CLK | /* Wait time: 2*SCY */\
- ORxG_TRLX)
+#define CFG_FIOX_OR7 (P2SZ_TO_AM(CFG_FIOX_SIZE) |\
+ ORxG_ACS_DIV4 |\
+ ORxG_SCY_5_CLK |\
+ ORxG_TRLX)
-/* CS8 - DOH Master
+/* CS8 - FPGA DOH Master
*/
-#define CFG_DOH_BR8 ((CFG_FDOHM_BASE & BRx_BA_MSK)|\
- BRx_PS_16 |\
- BRx_MS_GPCM_P |\
- BRx_V)
+#define CFG_FDOHM_BR8 ((CFG_FDOHM_BASE & BRx_BA_MSK) |\
+ BRx_PS_16 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
-#define CFG_DOH_OR8 (P2SZ_TO_AM(CFG_FDOHM_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV4 |\
- ORxG_SCY_5_CLK | /* Wait time: 2*SCY */\
- ORxG_TRLX)
+#define CFG_FDOHM_OR8 (P2SZ_TO_AM(CFG_FDOHM_SIZE) |\
+ ORxG_ACS_DIV4 |\
+ ORxG_SCY_5_CLK |\
+ ORxG_TRLX)
/* FPGA configuration */
-#define CFG_PC_FIOX_PROG (1 << (31- 5)) /* PD 5 */
-#define CFG_PC_FIOX_DONE (1 << (31-28)) /* PD 28 */
-#define CFG_PC_FIOX_INIT (1 << (31-29)) /* PD 29 */
+#define CFG_PD_FIOX_PROG (1 << (31- 5)) /* PD 5 */
+#define CFG_PD_FIOX_DONE (1 << (31-28)) /* PD 28 */
+#define CFG_PD_FIOX_INIT (1 << (31-29)) /* PD 29 */
-#define CFG_PC_FDOHM_PROG (1 << (31- 4)) /* PD 4 */
-#define CFG_PC_FDOHM_DONE (1 << (31-26)) /* PD 26 */
-#define CFG_PC_FDOHM_INIT (1 << (31-27)) /* PD 27 */
+#define CFG_PD_FDOHM_PROG (1 << (31- 4)) /* PD 4 */
+#define CFG_PD_FDOHM_DONE (1 << (31-26)) /* PD 26 */
+#define CFG_PD_FDOHM_INIT (1 << (31-27)) /* PD 27 */
#endif /* __CONFIG_H */
+
#if defined(CONFIG_CANBT) || \
defined(CONFIG_CCM) || \
- defined(CONFIG_SCM) || \
defined(CONFIG_CPCI405) || \
defined(CONFIG_CPCIISER4) || \
defined(CONFIG_DU405) || \
#if defined(CONFIG_NX823) || \
defined(CONFIG_CCM) || \
- defined(CONFIG_SCM) || \
defined(CONFIG_TQM8xxL) || \
defined(CONFIG_TQM8260)
void load_sernum_ethaddr(bd_t *bd);
projects / users / rw / ppcboot.git / commitdiff