{
        struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
        int ret, i, phy_mode = -1;
+       u32 mask;
 
        /* Make sure that port 0 is the cpu port */
        if (!dsa_is_cpu_port(ds, 0)) {
        if (ret < 0)
                return ret;
 
-       /* Enable CPU Port */
+       /* Enable CPU Port, force it to maximum bandwidth and full-duplex */
+       mask = QCA8K_PORT_STATUS_SPEED_1000 | QCA8K_PORT_STATUS_TXFLOW |
+              QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_DUPLEX;
+       qca8k_write(priv, QCA8K_REG_PORT_STATUS(QCA8K_CPU_PORT), mask);
        qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
                      QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
        qca8k_port_set_status(priv, QCA8K_CPU_PORT, 1);
 
 #define QCA8K_GOL_MAC_ADDR0                            0x60
 #define QCA8K_GOL_MAC_ADDR1                            0x64
 #define QCA8K_REG_PORT_STATUS(_i)                      (0x07c + (_i) * 4)
-#define   QCA8K_PORT_STATUS_SPEED                      GENMASK(2, 0)
-#define   QCA8K_PORT_STATUS_SPEED_S                    0
+#define   QCA8K_PORT_STATUS_SPEED                      GENMASK(1, 0)
+#define   QCA8K_PORT_STATUS_SPEED_10                   0
+#define   QCA8K_PORT_STATUS_SPEED_100                  0x1
+#define   QCA8K_PORT_STATUS_SPEED_1000                 0x2
 #define   QCA8K_PORT_STATUS_TXMAC                      BIT(2)
 #define   QCA8K_PORT_STATUS_RXMAC                      BIT(3)
 #define   QCA8K_PORT_STATUS_TXFLOW                     BIT(4)