drm/i915: pass dev_priv explicitly to PFIT_CONTROL

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PFIT_CONTROL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/fad44d3d987d914c83844cdf172adaa19772e035.1717514638.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e7ee4970e306d88867b60e901c8a652ad79719a1..49672694293ffd94e414c33ee51308368b8e72f5 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1861,12 +1861,13 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
         * according to register description and PRM.
         */
        drm_WARN_ON(&dev_priv->drm,
-                   intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
+                   intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_ENABLE);
        assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
 
        intel_de_write(dev_priv, PFIT_PGM_RATIOS,
                       crtc_state->gmch_pfit.pgm_ratios);
-       intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
+       intel_de_write(dev_priv, PFIT_CONTROL(dev_priv),
+                      crtc_state->gmch_pfit.control);
 
        /* Border color in case we don't scale up to the full screen. Black by
         * default, change to something else for debugging. */
@@ -2195,8 +2196,8 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
        assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
 
        drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
-                   intel_de_read(dev_priv, PFIT_CONTROL));
-       intel_de_write(dev_priv, PFIT_CONTROL, 0);
+                   intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)));
+       intel_de_write(dev_priv, PFIT_CONTROL(dev_priv), 0);
 }
 
 static void i9xx_crtc_disable(struct intel_atomic_state *state,
@@ -2974,7 +2975,7 @@ static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
        if (!i9xx_has_pfit(dev_priv))
                return;
 
-       tmp = intel_de_read(dev_priv, PFIT_CONTROL);
+       tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv));
        if (!(tmp & PFIT_ENABLE))
                return;
 

diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 891777481dd9084469dca282e62cc8da661a659f..9f018503d4fd6eb68f3dfbe135f684615eee0dc0 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -148,7 +148,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
 
        /* gen2/3 store dither state in pfit control, needs to match */
        if (DISPLAY_VER(dev_priv) < 4) {
-               tmp = intel_de_read(dev_priv, PFIT_CONTROL);
+               tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv));
 
                crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE;
        }

diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index b97087f8e3119e73ed11daa1efb09bdae6d429a6..b81046a6d36959d6b1e5b0ff97e03b0cb911e411 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -950,7 +950,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
        } else {
                u32 tmp;
 
-               if (intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_VERT_AUTO_SCALE)
+               if (intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_VERT_AUTO_SCALE)
                        tmp = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);
                else
                        tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 710078a6bf3f8077de113efa26f2219d4ea307e3..ca3d43e5061a43bfc7132db08ca628e1a03bc769 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1507,7 +1507,7 @@
 #define   VIDEO_DIP_ENABLE_AS_ADL      REG_BIT(23)
 
 /* Panel fitting */
-#define PFIT_CONTROL   _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
+#define PFIT_CONTROL(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
 #define   PFIT_ENABLE                  REG_BIT(31)
 #define   PFIT_PIPE_MASK               REG_GENMASK(30, 29) /* 965+ */
 #define   PFIT_PIPE(pipe)              REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe))