Modifications for 1.1.4:
======================================================================
+* Fix Sandpoint8240 port: boots now from flash, without need for DINK
+
* "Final" fix for HUSH shell
* Fix IDE on BAB750 board
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ns16550.o ns87308.o serial.o speed.o
-SOBJS = early_init.o
+OBJS = $(BOARD).o flash.o ns16550.o ns87308.o serial.o speed.o \
+ pci.o eepro100.o
-$(LIB): .depend $(OBJS) $(SOBJS)
+$(LIB): .depend $(OBJS)
$(AR) crv $@ $^
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+.depend: Makefile $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
sinclude .depend
# Sandpoint boards
#
-#TEXT_BASE = 0xFE000000
-TEXT_BASE = 0x00090000
+#TEXT_BASE = 0x00090000
+TEXT_BASE = 0xFFF00000
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
--- /dev/null
+#include <ppcboot.h>
+#include <mpc824x.h>
+#include <net.h>
+
+#include "pci.h"
+
+ /* Ethernet chip registers.
+ */
+#define SCBStatus 0 /* Rx/Command Unit Status *Word* */
+#define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */
+#define SCBCmd 2 /* Rx/Command Unit Command *Word* */
+#define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */
+#define SCBPointer 4 /* General purpose pointer. */
+#define SCBPort 8 /* Misc. commands and operands. */
+#define SCBflash 12 /* Flash memory control. */
+#define SCBeeprom 14 /* EEPROM memory control. */
+#define SCBCtrlMDI 16 /* MDI interface control. */
+#define SCBEarlyRx 20 /* Early receive byte count. */
+#define SCBGenControl 28 /* 82559 General Control Register */
+#define SCBGenStatus 29 /* 82559 General Status register */
+
+ /* 82559 SCB status word defnitions
+ */
+#define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */
+#define SCB_STATUS_FR 0x4000 /* frame received */
+#define SCB_STATUS_CNA 0x2000 /* CU left active state */
+#define SCB_STATUS_RNR 0x1000 /* receiver left ready state */
+#define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */
+#define SCB_STATUS_SWI 0x0400 /* software generated interrupt */
+#define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */
+
+#define SCB_INTACK_MASK 0xFD00 /* all the above */
+
+#define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
+#define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
+
+ /* System control block commands
+ */
+/* CU Commands */
+#define CU_NOP 0x0000
+#define CU_START 0x0010
+#define CU_RESUME 0x0020
+#define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */
+#define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
+#define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */
+#define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
+
+/* RUC Commands */
+#define RUC_NOP 0x0000
+#define RUC_START 0x0001
+#define RUC_RESUME 0x0002
+#define RUC_ABORT 0x0004
+#define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */
+#define RUC_RESUMENR 0x0007
+
+#define CU_CMD_MASK 0x00f0
+#define RU_CMD_MASK 0x0007
+
+#define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */
+#define SCB_SWI 0x0200 /* 1 - cause device to interrupt */
+
+#define CU_STATUS_MASK 0x00C0
+#define RU_STATUS_MASK 0x003C
+
+#define RU_STATUS_IDLE (0<<2)
+#define RU_STATUS_SUS (1<<2)
+#define RU_STATUS_NORES (2<<2)
+#define RU_STATUS_READY (4<<2)
+#define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2))
+#define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))
+#define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))
+
+ /* 82559 Port interface commands.
+ */
+#define I82559_RESET 0x00000000 /* Software reset */
+#define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */
+#define I82559_SELECTIVE_RESET 0x00000002
+#define I82559_DUMP 0x00000003
+#define I82559_DUMP_WAKEUP 0x00000007
+
+ /* 82559 Eeprom interface.
+ */
+#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
+#define EE_CS 0x02 /* EEPROM chip select. */
+#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
+#define EE_WRITE_0 0x01
+#define EE_WRITE_1 0x05
+#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
+#define EE_ENB (0x4800 | EE_CS)
+
+ /* The EEPROM commands include the alway-set leading bit.
+ */
+#define EE_WRITE_CMD (5 << addr_len)
+#define EE_READ_CMD (6 << addr_len)
+#define EE_ERASE_CMD (7 << addr_len)
+
+ /* Receive frame descriptors.
+ */
+struct RxFD {
+ volatile u16 status;
+ volatile u16 control;
+ volatile u32 link; /* struct RxFD * */
+ volatile u32 rx_buf_addr; /* void * */
+ volatile u32 count;
+
+ volatile u8 data[PKTSIZE_ALIGN];
+};
+
+#define RFD_STATUS_C 0x8000 /* completion of received frame */
+#define RFD_STATUS_OK 0x2000 /* frame received with no errors */
+
+#define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */
+#define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */
+#define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */
+#define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */
+
+#define RFD_COUNT_MASK 0x3fff
+#define RFD_COUNT_F 0x4000
+#define RFD_COUNT_EOF 0x8000
+
+#define RFD_RX_CRC 0x0800 /* crc error */
+#define RFD_RX_ALIGNMENT 0x0400 /* alignment error */
+#define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */
+#define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */
+#define RFD_RX_SHORT 0x0080 /* short frame error */
+#define RFD_RX_LENGTH 0x0020
+#define RFD_RX_ERROR 0x0010 /* receive error */
+#define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */
+#define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */
+#define RFD_RX_TCO 0x0001 /* TCO indication */
+
+ /* Transmit frame descriptors
+ */
+struct TxFD { /* Transmit frame descriptor set. */
+ volatile u16 status;
+ volatile u16 command;
+ volatile u32 link; /* void * */
+ volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */
+ volatile s32 count;
+
+ volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */
+ volatile s32 tx_buf_size0; /* Length of Tx frame. */
+ volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */
+ volatile s32 tx_buf_size1; /* Length of Tx frame. */
+};
+
+#define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */
+#define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
+#define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
+#define TxCB_CMD_I 0x2000 /* generate interrupt on completion */
+#define TxCB_CMD_S 0x4000 /* suspend on completion */
+#define TxCB_CMD_EL 0x8000 /* last command block in CBL */
+
+#define TxCB_COUNT_MASK 0x3fff
+#define TxCB_COUNT_EOF 0x8000
+
+ /* The Speedo3 Rx and Tx frame/buffer descriptors.
+ */
+struct descriptor { /* A generic descriptor. */
+ volatile u16 status;
+ volatile u16 command;
+ volatile u32 link; /* struct descriptor * */
+
+ unsigned char params[0];
+};
+
+#define CFG_CMD_EL 0x8000
+#define CFG_CMD_SUSPEND 0x4000
+#define CFG_CMD_INT 0x2000
+#define CFG_CMD_IAS 0x0001 /* individual address setup */
+#define CFG_CMD_CONFIGURE 0x0002 /* configure */
+
+#define CFG_STATUS_C 0x8000
+#define CFG_STATUS_OK 0x2000
+
+ /* Misc.
+ */
+#define NUM_RX_DESC PKTBUFSRX
+#define NUM_TX_DESC 1 /* Number of TX descriptors */
+
+#define TOUT_LOOP 1000000
+
+#define ETH_ALEN 6
+
+static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
+static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
+static int rx_next; /* RX descriptor ring pointer */
+static int tx_next; /* TX descriptor ring pointer */
+static int tx_threshold;
+
+static u_long iobase = 0;
+
+static void init_rx_ring(void);
+static void purge_tx_ring(void);
+
+static void check_hw_addr(bd_t * bis);
+
+static inline int INL(u_long addr)
+{
+ return le32_to_cpu(*(volatile u32 *)(addr + iobase));
+}
+
+static inline int INW(u_long addr)
+{
+ return le16_to_cpu(*(volatile u16 *)(addr + iobase));
+}
+
+static inline int INB(u_long addr)
+{
+ return *(volatile u8 *)(addr + iobase);
+}
+
+static inline void OUTB(int command, u_long addr)
+{
+ *(volatile u8 *)(addr + iobase) = command;
+}
+
+static inline void OUTW(int command, u_long addr)
+{
+ *(volatile u16 *)(addr + iobase) = cpu_to_le16(command);
+}
+
+static inline void OUTL(int command, u_long addr)
+{
+ *(volatile u32 *)(addr + iobase) = cpu_to_le32(command);
+}
+
+ /* Wait for the chip get the command.
+ */
+static int wait_for_eepro100(void)
+{
+ int i;
+
+ for(i = 0; INW(SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++)
+ {
+ if (i >= TOUT_LOOP)
+ {
+ return 0;
+ }
+ }
+
+ return 1;
+}
+
+int eth_init(bd_t *bis)
+{
+ int i, status = 0;
+ int bus, devno, func;
+ int tx_cur;
+ struct descriptor *ias_cmd;
+
+ /* Find PCI device
+ */
+ if (pci_dev_find(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_82557,
+ 0, &bus, &devno, &func) != TRUE)
+ {
+ printf("Error: Can not find an ethernet card on the PCI bus\n");
+ goto Done;
+ }
+
+ pci_config_inl(bus, devno, func, PCI_CFG_BASE_ADDRESS_0, &iobase);
+ iobase &= PCI_MEMBASE_MASK;
+
+ printf("eth: Intel i82559 PCI EtherExpressPro @0x%x"
+ "(bus=%d, device=%d, func=%d)\n",
+ iobase, bus, devno, func);
+
+ pci_config_outl (bus, devno, func,
+ PCI_CFG_COMMAND,
+ PCI_CMD_MEM_ENABLE |
+ PCI_CMD_MASTER_ENABLE);
+
+ /* Check if I/O accesses and Bus Mastering are enabled.
+ */
+ pci_config_inl(bus, devno, func, PCI_CFG_COMMAND, &status);
+ if (!(status & PCI_CMD_MEM_ENABLE))
+ {
+ printf("Error: Can not enable MEM access.\n");
+ goto Done;
+ }
+
+ if (!(status & PCI_CMD_MASTER_ENABLE))
+ {
+ printf("Error: Can not enable Bus Mastering.\n");
+ goto Done;
+ }
+
+ /* Set the latency timer for value.
+ */
+ pci_config_outb(bus, devno, func,
+ PCI_CFG_LATENCY_TIMER,
+ PCI_LATENCY_TIMER);
+
+ udelay(10 * 1000);
+
+ check_hw_addr(bis);
+
+ /* Reset the ethernet controller
+ */
+ OUTL(I82559_SELECTIVE_RESET, SCBPort);
+ udelay(20);
+
+ OUTL(I82559_RESET, SCBPort);
+ udelay(20);
+
+ if (!wait_for_eepro100())
+ {
+ printf("Error: Can not reset ethernet controller.\n");
+ goto Done;
+ }
+ OUTL(0, SCBPointer);
+ OUTW(SCB_M | RUC_ADDR_LOAD, SCBCmd);
+
+ if (!wait_for_eepro100())
+ {
+ printf("Error: Can not reset ethernet controller.\n");
+ goto Done;
+ }
+ OUTL(0, SCBPointer);
+ OUTW(SCB_M | CU_ADDR_LOAD, SCBCmd);
+
+ /* Initialize Rx and Tx rings.
+ */
+ init_rx_ring();
+ purge_tx_ring();
+
+ /* Tell the adapter where the RX ring is located.
+ */
+ if (!wait_for_eepro100())
+ {
+ printf("Error: Can not reset ethernet controller.\n");
+ goto Done;
+ }
+
+ OUTL((u32) &rx_ring[rx_next], SCBPointer);
+ OUTW(SCB_M | RUC_START, SCBCmd);
+
+ /* Send the Individual Address Setup frame
+ */
+ tx_cur = tx_next;
+ tx_next = ((tx_next+1) % NUM_TX_DESC);
+
+ ias_cmd = (struct descriptor *)&tx_ring[tx_cur];
+ ias_cmd->command = cpu_to_le16((CFG_CMD_SUSPEND | CFG_CMD_IAS));
+ ias_cmd->status = 0;
+ ias_cmd->link = cpu_to_le32((u32) &tx_ring[tx_next]);
+
+ memcpy(ias_cmd->params, bis->bi_enetaddr, 6);
+
+ /* Tell the adapter where the TX ring is located.
+ */
+ if (!wait_for_eepro100())
+ {
+ printf("Error: Can not reset ethernet controller.\n");
+ goto Done;
+ }
+
+ OUTL((u32) &tx_ring[tx_cur], SCBPointer);
+ OUTW(SCB_M | CU_START, SCBCmd);
+
+ for (i=0; !(le16_to_cpu(tx_ring[tx_cur].status) & CFG_STATUS_C); i++)
+ {
+ if (i >= TOUT_LOOP)
+ {
+ printf("eth: Tx error buffer not ready\n");
+ goto Done;
+ }
+ }
+
+ if (!(le16_to_cpu(tx_ring[tx_cur].status) & CFG_STATUS_OK))
+ {
+ printf("TX error status = 0x%08X\n",
+ le16_to_cpu(tx_ring[tx_cur].status));
+ status++;
+ }
+
+Done:
+ return status;
+}
+
+int eth_send(volatile void *packet, int length)
+{
+ int i, status = 0;
+ int tx_cur;
+
+ if (length <= 0)
+ {
+ printf("eth: bad packet size: %d\n", length);
+ goto Done;
+ }
+
+ tx_cur = tx_next;
+ tx_next = (tx_next+1) % NUM_TX_DESC;
+
+ tx_ring[tx_cur].command = cpu_to_le16(TxCB_CMD_TRANSMIT | TxCB_CMD_SF | \
+ TxCB_CMD_S | TxCB_CMD_EL);
+ tx_ring[tx_cur].status = 0;
+ tx_ring[tx_cur].count = cpu_to_le32(tx_threshold);
+ tx_ring[tx_cur].link = cpu_to_le32((u32) &tx_ring[tx_next]);
+ tx_ring[tx_cur].tx_desc_addr = cpu_to_le32((u32) &tx_ring[tx_cur].tx_buf_addr0);
+ tx_ring[tx_cur].tx_buf_addr0 = cpu_to_le32((u_long)packet);
+ tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32(length);
+
+ if (!wait_for_eepro100())
+ {
+ printf("eth: Tx error ethernet controller not ready.\n");
+ goto Done;
+ }
+
+ /* Send the packet.
+ */
+ OUTL((u32) &tx_ring[tx_cur], SCBPointer);
+ OUTW(SCB_M | CU_START, SCBCmd);
+
+ for(i = 0; !(le16_to_cpu(tx_ring[tx_cur].status) & CFG_STATUS_C); i++)
+ {
+ if (i >= TOUT_LOOP)
+ {
+ printf("eth: Tx error buffer not ready\n");
+ goto Done;
+ }
+ }
+
+ if (!(le16_to_cpu(tx_ring[tx_cur].status) & CFG_STATUS_OK))
+ {
+ printf("TX error status = 0x%08X\n",
+ le16_to_cpu(tx_ring[tx_cur].status));
+ status++;
+ }
+
+ Done:
+ return status;
+}
+
+int eth_rx(void)
+{
+ u16 status, stat;
+ int rx_prev, length = 0;
+
+ stat = INW(SCBStatus);
+ OUTW(stat & SCB_STATUS_RNR, SCBStatus);
+
+ for ( ; ; )
+ {
+ status = le16_to_cpu(rx_ring[rx_next].status);
+
+ if (!(status & RFD_STATUS_C))
+ {
+ break;
+ }
+
+ /* Valid frame status.
+ */
+ if ((status & RFD_STATUS_OK))
+ {
+ /* A valid frame received.
+ */
+ length = le32_to_cpu(rx_ring[rx_next].count) & 0x3fff;
+
+ /* Pass the packet up to the protocol
+ * layers.
+ */
+ NetReceive(rx_ring[rx_next].data, length);
+ }
+ else
+ {
+ /* There was an error.
+ */
+ printf("RX error status = 0x%08X\n", status);
+ }
+
+ rx_ring[rx_next].control = cpu_to_le16(RFD_CONTROL_S);
+ rx_ring[rx_next].status = 0;
+ rx_ring[rx_next].count = cpu_to_le32(PKTSIZE_ALIGN << 16);
+
+ rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
+ rx_ring[rx_prev].control = 0;
+
+ /* Update entry information.
+ */
+ rx_next = (rx_next + 1) % NUM_RX_DESC;
+ }
+
+ if (stat & SCB_STATUS_RNR)
+ {
+
+ printf("eth: Receiver is not ready, restart it !\n");
+
+ /* Reinitialize Rx ring.
+ */
+ init_rx_ring();
+
+ if (!wait_for_eepro100())
+ {
+ printf("Error: Can not restart ethernet controller.\n");
+ goto Done;
+ }
+
+ OUTL((u32) &rx_ring[rx_next], SCBPointer);
+ OUTW(SCB_M | RUC_START, SCBCmd);
+ }
+
+ Done:
+ return length;
+}
+
+void eth_halt(void)
+{
+ if (!iobase)
+ {
+ goto Done;
+ }
+
+ /* Reset the ethernet controller
+ */
+ OUTL(I82559_SELECTIVE_RESET, SCBPort);
+ udelay(20);
+
+ OUTL(I82559_RESET, SCBPort);
+ udelay(20);
+
+ if (!wait_for_eepro100())
+ {
+ printf("Error: Can not reset ethernet controller.\n");
+ goto Done;
+ }
+ OUTL(0, SCBPointer);
+ OUTW(SCB_M | RUC_ADDR_LOAD, SCBCmd);
+
+ if (!wait_for_eepro100())
+ {
+ printf("Error: Can not reset ethernet controller.\n");
+ goto Done;
+ }
+ OUTL(0, SCBPointer);
+ OUTW(SCB_M | CU_ADDR_LOAD, SCBCmd);
+
+ Done:
+ return;
+}
+
+ /* SROM Read.
+ */
+static int read_eeprom(long iobase, int location, int addr_len)
+{
+ unsigned short retval = 0;
+ int read_cmd = location | EE_READ_CMD;
+ int i;
+
+ OUTW(EE_ENB & ~EE_CS, SCBeeprom);
+ OUTW(EE_ENB, SCBeeprom);
+
+ /* Shift the read command bits out. */
+ for (i = 12; i >= 0; i--)
+ {
+ short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
+ OUTW(EE_ENB | dataval, SCBeeprom);
+ udelay(1);
+ OUTW(EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
+ udelay(1);
+ }
+ OUTW(EE_ENB, SCBeeprom);
+
+ for (i = 15; i >= 0; i--)
+ {
+ OUTW(EE_ENB | EE_SHIFT_CLK, SCBeeprom);
+ udelay(1);
+ retval = (retval << 1) |
+ ((INW(SCBeeprom) & EE_DATA_READ) ? 1 : 0);
+ OUTW(EE_ENB, SCBeeprom);
+ udelay(1);
+ }
+
+ /* Terminate the EEPROM access. */
+ OUTW(EE_ENB & ~EE_CS, SCBeeprom);
+ return retval;
+}
+
+static void init_rx_ring(void)
+{
+ int i;
+
+ for (i = 0; i < NUM_RX_DESC; i++)
+ {
+ rx_ring[i].status = 0;
+ rx_ring[i].control = (i == NUM_RX_DESC-1) ? cpu_to_le16(RFD_CONTROL_S) : 0;
+ rx_ring[i].link = cpu_to_le32((u32) &rx_ring[(i+1) % NUM_RX_DESC]);
+ rx_ring[i].rx_buf_addr = 0xffffffff;
+ rx_ring[i].count = cpu_to_le32(PKTSIZE_ALIGN << 16);
+ }
+
+ rx_next = 0;
+}
+
+static void purge_tx_ring(void)
+{
+ int i;
+
+ tx_next = 0;
+ tx_threshold = 0x01208000;
+
+ for (i = 0; i < NUM_TX_DESC; i++)
+ {
+ tx_ring[i].status = 0;
+ tx_ring[i].command = 0;
+ tx_ring[i].link = 0;
+ tx_ring[i].tx_desc_addr = 0;
+ tx_ring[i].count = 0;
+
+ tx_ring[i].tx_buf_addr0 = 0;
+ tx_ring[i].tx_buf_size0 = 0;
+ tx_ring[i].tx_buf_addr1 = 0;
+ tx_ring[i].tx_buf_size1 = 0;
+ }
+}
+
+static void check_hw_addr(bd_t *bis)
+{
+ u16 eeprom[0x40];
+ u16 sum = 0;
+ u8 hw_addr[ETH_ALEN];
+ int i, j;
+ int addr_len = read_eeprom(iobase, 0, 6) == 0xffff ? 8 : 6;
+
+ for (j = 0, i = 0; i < 0x40; i++)
+ {
+ u16 value = read_eeprom(iobase, i, addr_len);
+ eeprom[i] = value;
+ sum += value;
+ if (i < 3)
+ {
+ hw_addr[j++] = value;
+ hw_addr[j++] = value >> 8;
+ }
+ }
+
+ if (sum != 0xBABA)
+ printf("eth: Invalid EEPROM checksum %#4.4x, "
+ "check settings before activating this device!\n",
+ sum);
+
+ for (i=0;i<ETH_ALEN;i++)
+ {
+ if (hw_addr[i] != bis->bi_enetaddr[i])
+ {
+ printf("Warning: HW address don't match:\n");
+ printf("Address in SROM is "
+ "%02X:%02X:%02X:%02X:%02X:%02X\n",
+ hw_addr[0], hw_addr[1], hw_addr[2],
+ hw_addr[3], hw_addr[4], hw_addr[5]);
+ printf("Address used by ppcboot is "
+ "%02X:%02X:%02X:%02X:%02X:%02X\n",
+ bis->bi_enetaddr[0], bis->bi_enetaddr[1],
+ bis->bi_enetaddr[2], bis->bi_enetaddr[3],
+ bis->bi_enetaddr[4], bis->bi_enetaddr[5]);
+ goto Done;
+ }
+ }
+
+Done:
+ return;
+}
/*flash command address offsets*/
+#if 0
#define ADDR0 (0x555)
#define ADDR1 (0x2AA)
#define ADDR3 (0x001)
+#else
+#define ADDR0 (0xAAA)
+#define ADDR1 (0x555)
+#define ADDR3 (0x001)
+#endif
#define FLASH_WORD_SIZE unsigned char
static const map_entry chip_map[] =
{
- {AMD_ID_F040B, FLASH_AM040}
+ {AMD_ID_F040B, FLASH_AM040},
+ {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB}
};
const map_entry *p;
flash_info_t * const pflinfo = &flash_info[i];
const unsigned long base_address = flash_banks[i];
volatile FLASH_WORD_SIZE * const flash = (FLASH_WORD_SIZE *) base_address;
+ volatile FLASH_WORD_SIZE * addr2;
+#if 0
/* write autoselect sequence */
flash[0x5555] = 0xaa;
flash[0x2aaa] = 0x55;
flash[0x5555] = 0x90;
+#else
+ flash[0xAAA] = 0xaa;
+ flash[0x555] = 0x55;
+ flash[0xAAA] = 0x90;
+#endif
__asm__ __volatile__("sync");
+#if 0
pflinfo->flash_id = flash_id(flash[0x0], flash[0x1]);
+#else
+ pflinfo->flash_id = flash_id(flash[0x0], flash[0x2]);
+#endif
switch(pflinfo->flash_id & FLASH_TYPEMASK)
{
pflinfo->protect[i] = flash[(i << 16) | 0x2];
}
break;
+ case FLASH_STM800AB:
+ pflinfo->size = 0x00100000;
+ pflinfo->sector_count = 19;
+ pflinfo->start[0] = base_address;
+ pflinfo->start[1] = base_address + 0x4000;
+ pflinfo->start[2] = base_address + 0x6000;
+ pflinfo->start[3] = base_address + 0x8000;
+ for(i = 1; i < 16; i++)
+ {
+ pflinfo->start[i+3] = base_address + 0x00010000 * i;
+ }
+ /* check for protected sectors */
+ for (i = 0; i < pflinfo->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile FLASH_WORD_SIZE *)(pflinfo->start[i]);
+ if (pflinfo->flash_id & FLASH_MAN_SST)
+ pflinfo->protect[i] = 0;
+ else
+ pflinfo->protect[i] = addr2[2] & 1;
+ }
+ break;
}
/* reset device to read mode */
{
case FLASH_MAN_AMD: mfct = "AMD"; break;
case FLASH_MAN_FUJ: mfct = "FUJITSU"; break;
+ case FLASH_MAN_STM: mfct = "STM"; break;
case FLASH_MAN_SST: mfct = "SST"; break;
case FLASH_MAN_BM: mfct = "Bright Microelectonics"; break;
case FLASH_MAN_INTEL: mfct = "Intel"; break;
case FLASH_AM160T: type = "AM29LV160T (16 Mbit, top boot sector)"; break;
case FLASH_AM320B: type = "AM29LV320B (32 Mbit, bottom boot sect)"; break;
case FLASH_AM320T: type = "AM29LV320T (32 Mbit, top boot sector)"; break;
+ case FLASH_STM800AB: type = "M29W800AB (8 Mbit, bottom boot sect)"; break;
case FLASH_SST800A: type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; break;
case FLASH_SST160A: type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; break;
}
"%s %08lX %s %s",
(i % 5) ? "" : "\n ",
info->start[i],
- erased ? "E" : " ",
+ erased ? "E" : " ",
info->protect[i] ? "RO" : " "
);
}
}
if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
+ (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
printf ("Can't erase unknown flash type - aborted\n");
return 1;
}
#define LDEV_RTC_APC 0x02 /*Real Time Clock and Advanced Power Control*/
#define LDEV_FDC 0x03 /*floppy disk controller*/
#define LDEV_PARP 0x04 /*Parallel port*/
-#define LDEV_UART1 0x05
-#define LDEV_UART2 0x06
+#define LDEV_UART2 0x05
+#define LDEV_UART1 0x06
#define LDEV_GPIO 0x07 /*General Purpose IO and chip select output signals*/
#define LDEV_POWRMAN 0x08 /*Power Managment*/
--- /dev/null
+/*
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001
+ * James Dougherty (jfd@cs.stanford.edu)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * PCI Configuration space access support for MPC824x/MPC107 PCI Bridge
+ */
+#include <ppcboot.h>
+#include "mpc824x.h"
+#include "pci.h"
+
+int numPciBus = 1; /* One bus: MPC107 Internal bridge */
+
+/*
+ *
+ * pci_dev_find - find the nth device with the given device & vendor ID
+ *
+ */
+int pci_dev_find(int vendorId, /* vendor ID */
+ int deviceId, /* device ID */
+ int index, /* desired instance of device */
+ int* pBusNo, /* bus number */
+ int* pDeviceNo, /* device number */
+ int* pFuncNo) /* function number */
+{
+ int status = ERROR;
+ int cont = TRUE;
+ int busNo;
+ int deviceNo;
+ int funcNo;
+ uint32 device;
+ uint32 vendor;
+ char header;
+
+ for (busNo = 0; cont == TRUE && busNo <= numPciBus; busNo++)
+ for (deviceNo = 0;
+ ((cont == TRUE) && (deviceNo < PCI_MAX_DEV));
+ ++deviceNo)
+ for (funcNo = 0; cont == TRUE && funcNo < PCI_MAX_FUNC; funcNo++){
+ /* avoid a special bus cycle */
+
+ if ((deviceNo == 0x1f) && (funcNo == 0x07))
+ continue;
+
+ pci_config_inl (busNo, deviceNo, funcNo, PCI_CFG_VENDOR_ID,
+ &vendor);
+
+ /*
+ * If nonexistent device, skip to next, only look at
+ * vendor ID field for existence check
+ */
+ if (((vendor & 0x0000ffff) == 0x0000FFFF) && (funcNo == 0))
+ break;
+ device = vendor >> 16;
+ device &= 0x0000FFFF;
+ vendor &= 0x0000FFFF;
+ if ((vendor == (uint32)vendorId) &&
+ (device == (uint32)deviceId) &&
+ (index-- == 0)){
+ *pBusNo = busNo;
+ *pDeviceNo = deviceNo;
+ *pFuncNo = funcNo;
+ status = OK;
+ cont = FALSE; /* terminate all loops */
+ continue;
+ }
+
+ /* goto next if current device is single function */
+
+ pci_config_inb (busNo, deviceNo, funcNo, PCI_CFG_HEADER_TYPE,
+ &header);
+ if ((header & PCI_HEADER_MULTI_FUNC) !=
+ PCI_HEADER_MULTI_FUNC && funcNo == 0)
+ break;
+ }
+
+ return status;
+}
+
+/*
+ *
+ * pci_class_find - find the nth occurence of a device by PCI class code.
+ *
+ * RETURNS:
+ * OK, or ERROR if the class didn't match.
+ */
+
+int pci_class_find(int classCode, /* 24-bit class code */
+ int index, /* desired instance of device */
+ int * pBusNo, /* bus number */
+ int * pDeviceNo, /* device number */
+ int * pFuncNo) /* function number */
+{
+ int status = ERROR;
+ int cont = TRUE;
+ int busNo;
+ int deviceNo;
+ int funcNo;
+ int classCodeReg;
+ int vendor;
+ char header;
+
+
+ for (busNo = 0; cont == TRUE && busNo <= numPciBus; busNo++)
+ for (deviceNo = 0;
+ ((cont == TRUE) && (deviceNo < PCI_MAX_DEV));
+ ++deviceNo)
+ for (funcNo = 0; cont == TRUE && funcNo < PCI_MAX_FUNC; funcNo++){
+
+ /* avoid a special bus cycle */
+ if ((deviceNo == 0x1f) && (funcNo == 0x07))
+ continue;
+
+ pci_config_inl (busNo, deviceNo, funcNo, PCI_CFG_VENDOR_ID,
+ &vendor);
+
+ /*
+ * If nonexistent device, skip to next, only look at
+ * vendor ID field for existence check
+ */
+ if (((vendor & 0x0000ffff) == 0x0000FFFF) && (funcNo == 0))
+ break;
+
+ pci_config_inl (busNo, deviceNo, funcNo, PCI_CFG_REVISION,
+ &classCodeReg);
+
+ if ((((classCodeReg >> 8) & 0x00ffffff) == classCode) &&
+ (index-- == 0))
+ {
+ *pBusNo = busNo;
+ *pDeviceNo = deviceNo;
+ *pFuncNo = funcNo;
+ status = OK;
+ cont = FALSE; /* terminate all loops */
+ continue;
+ }
+
+ /* goto next if current device is single function */
+
+ pci_config_inb (busNo, deviceNo, funcNo, PCI_CFG_HEADER_TYPE,
+ &header);
+ if ((header & PCI_HEADER_MULTI_FUNC) !=
+ PCI_HEADER_MULTI_FUNC && funcNo == 0)
+ break;
+ }
+ return status;
+}
+
+
+/*
+ *
+ * pci_dev_config - configure a device on a PCI bus
+ *
+ * This routine configures a device that is on a Peripheral Component
+ * Interconnect (PCI) bus by writing to the configuration header of the
+ * selected device.
+ *
+ * It first disables the device by clearing the command register in the
+ * configuration header. It then sets the I/O and/or memory space base
+ * address registers, the latency timer value and the cache line size.
+ * Finally, it re-enables the device by loading the command register with
+ * the specified command.
+ *
+ * NOTE: This routine is designed for Type 0 PCI Configuration Headers ONLY.
+ * It is NOT usable for configuring, for example, a PCI-to-PCI bridge.
+ *
+ * RETURNS: OK always.
+ */
+int pci_dev_config(int pciBusNo, /* PCI bus number */
+ int pciDevNo, /* PCI device number */
+ int pciFuncNo, /* PCI function number */
+ uint32 devIoBaseAdrs, /* device IO base address */
+ uint32 devMemBaseAdrs, /* device memory base address */
+ uint32 command) /* command to issue */
+{
+ int ix;
+ uint32 tmp32;
+
+ /*
+ * Disable device by clearing its command register field in its
+ * configuration header. Write 0 clears command and preserves status.
+ */
+ pci_config_outl (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_COMMAND, 0);
+
+ for (ix = PCI_CFG_BASE_ADDRESS_0; ix <= PCI_CFG_BASE_ADDRESS_5; ix+=4){
+
+ /* Write all f's and read back value */
+ pci_config_outl (pciBusNo, pciDevNo, pciFuncNo, ix, 0xffffffff);
+ pci_config_inl (pciBusNo, pciDevNo, pciFuncNo, ix, &tmp32);
+
+ if (tmp32 == 0){
+ /* No bar */
+ break;
+ }
+
+ /* I/O space requested */
+ if (tmp32 & 0x1){
+ pci_config_outl (pciBusNo, pciDevNo, pciFuncNo, ix,
+ devIoBaseAdrs | 0x1);
+ } else{
+ /* Memory space required, set specified base address */
+ pci_config_outl (pciBusNo, pciDevNo, pciFuncNo, ix,
+ devMemBaseAdrs & ~0x1);
+ }
+ }
+
+ /* Configure Cache Line Size Register */
+ pci_config_outb (pciBusNo, pciDevNo, pciFuncNo,
+ PCI_CFG_CACHE_LINE_SIZE,
+ PCI_CACHE_LINE_SIZE);
+
+ /* Configure Latency Timer */
+ pci_config_outb (pciBusNo, pciDevNo, pciFuncNo,
+ PCI_CFG_LATENCY_TIMER,
+ PCI_LATENCY_TIMER);
+
+ /*
+ * Enable the device's capabilities as specified, do not
+ * reset any status bits in doing so.
+ */
+ pci_config_modl (pciBusNo, pciDevNo, pciFuncNo,
+ PCI_CFG_COMMAND,
+ (PCI_CMD_MASK | command), command);
+
+ return OK;
+}
+
+
+/*
+ *
+ * pci_config_bdf_pack - pack parameters for the Configuration Address Register
+ *
+ * This routine packs three parameters into one integer for accessing the
+ * Configuration Address Register
+ *
+ */
+
+int pci_config_bdf_pack(int busNo, /* bus number */
+ int deviceNo, /* device number */
+ int funcNo) /* function number */
+{
+ return (((busNo << 16) & 0x00ff0000) |
+ ((deviceNo << 11) & 0x0000f800) |
+ ((funcNo << 8) & 0x00000700));
+}
+
+/*
+ * pci_config_inb - read one byte from the PCI configuration space
+ *
+ * This routine reads one byte from the PCI configuration space
+ *
+ */
+int pci_config_inb(int busNo, /* bus number */
+ int deviceNo, /* device number */
+ int funcNo, /* function number */
+ int offset, /* offset into config space */
+ uint8 * pData) /* data read from the offset */
+{
+ uint8 retval = 0;
+ int retStat = ERROR;
+
+ mpc824x_mpc107_write32 (CHRP_REG_ADDR,
+ pci_config_bdf_pack (busNo, deviceNo, funcNo) |
+ (offset & 0xfc) | 0x80000000);
+ retval = mpc824x_mpc107_read8 (CHRP_REG_DATA + (offset & 0x3));
+ retStat = OK;
+
+ *pData = retval;
+
+ return retStat;
+}
+
+/*
+ *
+ * pci_config_inw - read one word from the PCI configuration space
+ *
+ * This routine reads one word from the PCI configuration space
+ *
+ */
+int pci_config_inw(int busNo, /* bus number */
+ int deviceNo, /* device number */
+ int funcNo, /* function number */
+ int offset, /* offset into config space */
+ uint16 * pData) /* data read from the offset */
+{
+ int retStat = ERROR;
+ uint16 retval = 0;
+
+ if (((offset & (int)0x1) > 0) ) {
+ return (retStat);
+ }
+
+ mpc824x_mpc107_write32 (CHRP_REG_ADDR,
+ pci_config_bdf_pack (busNo, deviceNo, funcNo) |
+ (offset & 0xfc) | 0x80000000);
+ retval = mpc824x_mpc107_read16 (CHRP_REG_DATA + (offset & 0x2));
+ retStat = OK;
+ *pData = retval;
+
+ return retStat;
+}
+
+/*
+ *
+ * pci_config_inl - read one longword from the PCI configuration space
+ *
+ * This routine reads one longword from the PCI configuration space
+ *
+ */
+int pci_config_inl(int busNo, /* bus number */
+ int deviceNo, /* device number */
+ int funcNo, /* function number */
+ int offset, /* offset into config space */
+ uint32 * pData) /* data read from the offset */
+{
+ int retStat = ERROR;
+ uint32 retval = 0;
+
+ if (((offset & (int)0x3) > 0) ) {
+ return (retStat);
+ }
+ mpc824x_mpc107_write32 (CHRP_REG_ADDR,
+ pci_config_bdf_pack (busNo, deviceNo, funcNo) |
+ (offset & 0xfc) | 0x80000000);
+ retval = mpc824x_mpc107_read32 (CHRP_REG_DATA);
+ asm volatile ("eieio");
+ retStat = OK;
+ *pData = retval;
+ return retStat;
+}
+
+/*
+ * pci_config_outb - write one byte to the PCI configuration space
+ *
+ * This routine writes one byte to the PCI configuration space.
+ *
+ */
+int pci_config_outb(int busNo, /* bus number */
+ int deviceNo, /* device number */
+ int funcNo, /* function number */
+ int offset, /* offset into config space */
+ uint8 data) /* data written to the offset */
+{
+
+ mpc824x_mpc107_write32 (CHRP_REG_ADDR,
+ pci_config_bdf_pack (busNo, deviceNo, funcNo) |
+ (offset & 0xfc) | 0x80000000);
+ mpc824x_mpc107_write8 ((CHRP_REG_DATA + (offset & 0x3)), data);
+ return OK;
+}
+
+/*
+ * pci_config_outw - write one 16-bit word to the PCI configuration space
+ *
+ * This routine writes one 16-bit word to the PCI configuration space.
+ *
+ * RETURNS: OK, or ERROR if this library is not initialized
+ */
+int pci_config_outw(int busNo, /* bus number */
+ int deviceNo, /* device number */
+ int funcNo, /* function number */
+ int offset, /* offset into config space */
+ uint16 data) /* data written to the offset */
+{
+ if (((offset & (int)0x1) > 0) ){
+ return (ERROR);
+ }
+
+ mpc824x_mpc107_write32 (CHRP_REG_ADDR,
+ pci_config_bdf_pack (busNo, deviceNo, funcNo) |
+ (offset & 0xfc) | 0x80000000);
+ mpc824x_mpc107_write16 ((CHRP_REG_DATA + (offset & 0x2)), data);
+ return OK;
+}
+
+
+/*
+ *
+ * pci_config_outl - write one longword to the PCI configuration space
+ *
+ * This routine writes one longword to the PCI configuration space.
+ *
+ */
+int pci_config_outl(int busNo, /* bus number */
+ int deviceNo, /* device number */
+ int funcNo, /* function number */
+ int offset, /* offset into config space */
+ uint32 data) /* data written to the offset */
+{
+ if (((offset & (int)0x3) > 0) ){
+ return (ERROR);
+ }
+ mpc824x_mpc107_write32 (CHRP_REG_ADDR,
+ pci_config_bdf_pack (busNo, deviceNo, funcNo) |
+ (offset & 0xfc) | 0x80000000);
+ mpc824x_mpc107_write32 (CHRP_REG_DATA, data);
+ asm volatile ("eieio");
+ return OK;
+}
+
+
+/*
+ *
+ * pci_config_modl - Perform a masked longword register update
+ *
+ * This function writes a field into a PCI configuration header without
+ * altering any bits not present in the field. It does this by first
+ * doing a PCI configuration read (into a temporary location) of the PCI
+ * configuration header word which contains the field to be altered.
+ * It then alters the bits in the temporary location to match the desired
+ * value of the field. It then writes back the temporary location with
+ * a configuration write. All configuration accesses are long and the
+ * field to alter is specified by the "1" bits in the 'bitMask' parameter.
+ *
+ */
+
+int pci_config_modl(int busNo, /* bus number */
+ int deviceNo, /* device number */
+ int funcNo, /* function number */
+ int offset, /* offset into config space */
+ uint32 bitMask, /* Mask of bits to alter */
+ uint32 data) /* data written to the offset */
+
+{
+ uint32 temp;
+ int stat;
+
+ if (((offset & (int)0x3) > 0) ){
+ return (ERROR);
+ }
+
+ stat = pci_config_inl (busNo, deviceNo, funcNo, offset, &temp);
+ if (stat == OK){
+ temp = (temp & ~bitMask) | (data & bitMask);
+ stat = pci_config_outl (busNo, deviceNo, funcNo, offset, temp);
+ }
+ return stat;
+}
+
+
+/*
+ *
+ * pci_config_modw - Perform a masked short register update
+ *
+ */
+int pci_config_modw(int busNo, /* bus number */
+ int deviceNo, /* device number */
+ int funcNo, /* function number */
+ int offset, /* offset into config space */
+ uint16 bitMask, /* Mask of bits to alter */
+ uint16 data) /* data written to the offset */
+{
+ uint16 temp;
+ int stat;
+ if (((offset & (int)0x1) > 0) ){
+ return (ERROR);
+ }
+ stat = pci_config_inw (busNo, deviceNo, funcNo, offset, &temp);
+ if (stat == OK){
+ temp = (temp & ~bitMask) | (data & bitMask);
+ stat = pci_config_outw (busNo, deviceNo, funcNo, offset, temp);
+ }
+ return stat;
+}
+
+
+
+/*
+ * pci_config_modb - Perform a masked byte register update
+ *
+ */
+int pci_config_modb(int busNo, /* bus number */
+ int deviceNo, /* device number */
+ int funcNo, /* function number */
+ int offset, /* offset into config space */
+ uint8 bitMask, /* Mask of bits to alter */
+ uint8 data) /* data written to the offset */
+{
+ uint8 temp;
+ int stat;
+ stat = pci_config_inb (busNo, deviceNo, funcNo, offset, &temp);
+ if (stat == OK){
+ temp = (temp & ~bitMask) | (data & bitMask);
+ stat = pci_config_outb (busNo, deviceNo, funcNo, offset, temp);
+ }
+ return stat;
+}
+
+/*
+ * pci_special_cycle - generate a special cycle with a message
+ */
+int
+pci_special_cycle(int busNo, /* bus number */
+ uint32 message) /* data driven onto AD[31:0] */
+{
+ int deviceNo = 0x0000001f;
+ int funcNo = 0x00000007;
+
+ mpc824x_mpc107_write32 (CHRP_REG_ADDR,
+ pci_config_bdf_pack (busNo, deviceNo, funcNo) |
+ 0x80000000);
+ mpc824x_mpc107_write32 (CHRP_REG_DATA, message);
+ return OK;
+}
+
+
+/*
+ * Find the extent of a PCI decode..
+ */
+unsigned int
+pci_size_bar(unsigned int base, unsigned long mask)
+{
+ uint32 size = mask & base; /* Find the significant bits */
+ size = size & ~(size-1); /* Get the lowest of them to find the decode size */
+ return size-1; /* extent = size - 1 */
+}
+
+/*
+ * Show/Init PCI devices on the specified bus number.
+ */
+int pci_dev_init(int busNo)
+{
+ int deviceNo, a;
+ uint32 cmd, bar;
+ int devices;
+ uint16 vendorId;
+ uint16 deviceId;
+ uint32 mbar0;
+ uint32 mbar1;
+ uint32 revId;
+ uint32 iline,ipin;
+
+ union {
+ int classCode;
+ char array[4];
+ } u;
+
+ printf("PCI: scanning bus%d ...\n", busNo);
+ printf(" bus dev fn venID devID class"
+ " rev MBAR0 MBAR1 IPIN ILINE\n");
+
+ devices = 0x1f;
+ for (deviceNo=0; deviceNo < devices; deviceNo++) {
+
+ /* Get device and vendor ID */
+ pci_config_inw (busNo, deviceNo, 0, PCI_CFG_VENDOR_ID, &vendorId);
+ pci_config_inw (busNo, deviceNo, 0, PCI_CFG_DEVICE_ID, &deviceId);
+
+ /* MPC107 Bridge */
+ if( deviceNo == 0x0){
+ /* Don't do anything */
+ }
+
+ /* Make sure IRQ's on PCI devices get configured correctly */
+ if( deviceNo == 0x0f){
+ /* Onboard */
+ pci_dev_config(busNo, deviceNo, 0,
+ PCI_ENET_IOADDR,
+ PCI_ENET_MEMADDR,
+ PCI_CMD_MEM_ENABLE |
+ PCI_CMD_MASTER_ENABLE);
+ } /* PCI Slot */
+
+ pci_config_inb (busNo, deviceNo, 0, PCI_CFG_PROGRAMMING_IF,
+ &u.array[3]);
+ pci_config_inb (busNo, deviceNo, 0, PCI_CFG_SUBCLASS, &u.array[2]);
+ pci_config_inb (busNo, deviceNo, 0, PCI_CFG_CLASS, &u.array[1]);
+ u.array[0] = 0;
+
+ pci_config_inl(busNo, deviceNo, 0, PCI_CFG_BASE_ADDRESS_0, &mbar0);
+ pci_config_inl(busNo, deviceNo, 0, PCI_CFG_BASE_ADDRESS_1, &mbar1);
+
+ pci_config_inl(busNo, deviceNo, 0, PCI_CFG_REVISION, &revId);
+ revId &= 0x000000ff;
+
+ pci_config_inl(busNo, deviceNo, 0, PCI_CFG_DEV_INT_LINE, &iline);
+ iline &= 0x000000ff;
+
+ pci_config_inl(busNo, deviceNo, 0, PCI_CFG_DEV_INT_LINE, &ipin);
+ ipin &= 0x0000ff00;
+ ipin >>= 8;
+
+
+ /* There are two ways to find out an empty device.
+ * 1. check Master Abort bit after the access.
+ * 2. check whether the read value is 0xffff.
+ * Since I didn't see the Master Abort bit of the host/PCI bridge
+ * changing, I use the second method.
+ */
+ if (vendorId != 0xffff)
+
+ printf(" %02x %02x %02x %04x %04x "
+ "%06x %02x %08x %08x %02x %02x\n",
+ busNo, deviceNo, 0,
+ vendorId, deviceId, u.classCode, revId,
+ mbar0, mbar1, ipin, iline);
+ }
+ return OK;
+}
+
+
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001
+ * James Dougherty (jfd@cs.stanford.edu)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __MPC824X_PCI
+#define __MPC824X_PCI
+
+/*
+ * PCI Configuration space Library and constants for MPC824x based
+ * systems.
+ */
+
+typedef unsigned char uint8;
+typedef unsigned int uint32;
+typedef unsigned short uint16;
+typedef int INT32;
+#define LOCAL static
+#define IMPORT extern
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+#define OK 1
+#define NONE 0
+#define ERROR -1
+#define TRUE 1
+#define FALSE (!TRUE)
+
+
+#define PCI_MAX_BUS 255
+#define PCI_MAX_DEV 32
+#define PCI_MAX_FUNC 8
+
+
+/* PCI Configuration I/O Addresses */
+#define PCI_CONFIG_ADDR 0x0cf8 /* write 32 bits to set address */
+#define PCI_CONFIG_DATA 0x0cfc /* 8, 16, or 32 bit accesses */
+#define PCI_CONFIG_CSE 0x0cf8 /* CSE register */
+#define PCI_CONFIG_FORWARD 0x0cfa /* forward register */
+#define PCI_CONFIG_BASE 0xc000 /* base register */
+
+/* PCI command bits */
+#define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */
+#define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */
+#define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */
+#define PCI_CMD_MON_ENABLE 0x0008 /* monitor special cycles enable */
+#define PCI_CMD_WI_ENABLE 0x0010 /* write and invalidate enable */
+#define PCI_CMD_SNOOP_ENABLE 0x0020 /* palette snoop enable */
+#define PCI_CMD_PERR_ENABLE 0x0040 /* parity error enable */
+#define PCI_CMD_WC_ENABLE 0x0080 /* wait cycle enable */
+#define PCI_CMD_SERR_ENABLE 0x0100 /* system error enable */
+#define PCI_CMD_FBTB_ENABLE 0x0200 /* fast back to back enable */
+
+/* PCI base address mask bits */
+
+#define PCI_MEMBASE_MASK ~0xf /* mask for memory base address */
+#define PCI_IOBASE_MASK ~0x3 /* mask for IO base address */
+#define PCI_BASE_IO 0x1 /* IO space indicator */
+#define PCI_BASE_BELOW_1M 0x2 /* memory locate below 1MB */
+#define PCI_BASE_IN_64BITS 0x4 /* memory locate anywhere in 64 bits */
+#define PCI_BASE_PREFETCH 0x8 /* memory prefetchable */
+
+/* Base Address Register Memory/IO Attribute bits */
+
+#define PCI_BAR_SPACE_MASK (0x01)
+#define PCI_BAR_SPACE_IO (0x01)
+#define PCI_BAR_SPACE_MEM (0x00)
+
+#define PCI_BAR_MEM_TYPE_MASK (0x06)
+#define PCI_BAR_MEM_ADDR32 (0x00)
+#define PCI_BAR_MEM_BELOW_1MB (0x02)
+#define PCI_BAR_MEM_ADDR64 (0x04)
+#define PCI_BAR_MEM_RESERVED (0x06)
+
+#define PCI_BAR_MEM_PREF_MASK (0x08)
+#define PCI_BAR_MEM_PREFETCH (0x08)
+#define PCI_BAR_MEM_NON_PREF (0x00)
+
+#define PCI_BAR_ALL_MASK (PCI_BAR_SPACE_MASK | \
+ PCI_BAR_MEM_TYPE_MASK | \
+ PCI_BAR_MEM_PREF_MASK)
+
+/* PCI header type bits */
+
+#define PCI_HEADER_TYPE_MASK 0x7f /* mask for header type */
+#define PCI_HEADER_PCI_PCI 0x01 /* PCI to PCI bridge */
+#define PCI_HEADER_TYPE0 0x00 /* normal device header */
+#define PCI_HEADER_MULTI_FUNC 0x80 /* multi function device */
+
+/* PCI configuration device and driver */
+
+#define SNOOZE_MODE 0x40 /* snooze mode */
+#define SLEEP_MODE_DIS 0x00 /* sleep mode disable */
+
+/* Standard device configuration register offsets */
+/* Note that only modulo-4 addresses are written to the address register */
+
+#define PCI_CFG_VENDOR_ID 0x00
+#define PCI_CFG_DEVICE_ID 0x02
+#define PCI_CFG_COMMAND 0x04
+#define PCI_CFG_STATUS 0x06
+#define PCI_CFG_REVISION 0x08
+#define PCI_CFG_PROGRAMMING_IF 0x09
+#define PCI_CFG_SUBCLASS 0x0a
+#define PCI_CFG_CLASS 0x0b
+#define PCI_CFG_CACHE_LINE_SIZE 0x0c
+#define PCI_CFG_LATENCY_TIMER 0x0d
+#define PCI_CFG_HEADER_TYPE 0x0e
+#define PCI_CFG_BIST 0x0f
+#define PCI_CFG_BASE_ADDRESS_0 0x10
+#define PCI_CFG_BASE_ADDRESS_1 0x14
+#define PCI_CFG_BASE_ADDRESS_2 0x18
+#define PCI_CFG_BASE_ADDRESS_3 0x1c
+#define PCI_CFG_BASE_ADDRESS_4 0x20
+#define PCI_CFG_BASE_ADDRESS_5 0x24
+#define PCI_CFG_CIS 0x28
+#define PCI_CFG_SUB_VENDER_ID 0x2c
+#define PCI_CFG_SUB_SYSTEM_ID 0x2e
+#define PCI_CFG_EXPANSION_ROM 0x30
+#define PCI_CFG_RESERVED_0 0x34
+#define PCI_CFG_RESERVED_1 0x38
+#define PCI_CFG_DEV_INT_LINE 0x3c
+#define PCI_CFG_DEV_INT_PIN 0x3d
+#define PCI_CFG_MIN_GRANT 0x3e
+#define PCI_CFG_MAX_LATENCY 0x3f
+#define PCI_CFG_SPECIAL_USE 0x41
+#define PCI_CFG_MODE 0x43
+
+
+/* PCI-to-PCI bridge configuration register offsets */
+/* Note that only modulo-4 addresses are written to the address register */
+
+#define PCI_CFG_PRIMARY_BUS 0x18
+#define PCI_CFG_SECONDARY_BUS 0x19
+#define PCI_CFG_SUBORDINATE_BUS 0x1a
+#define PCI_CFG_SEC_LATENCY 0x1b
+#define PCI_CFG_IO_BASE 0x1c
+#define PCI_CFG_IO_LIMIT 0x1d
+#define PCI_CFG_SEC_STATUS 0x1e
+#define PCI_CFG_MEM_BASE 0x20
+#define PCI_CFG_MEM_LIMIT 0x22
+#define PCI_CFG_PRE_MEM_BASE 0x24
+#define PCI_CFG_PRE_MEM_LIMIT 0x26
+#define PCI_CFG_PRE_MEM_BASE_U 0x28
+#define PCI_CFG_PRE_MEM_LIMIT_U 0x2c
+#define PCI_CFG_IO_BASE_U 0x30
+#define PCI_CFG_IO_LIMIT_U 0x32
+#define PCI_CFG_ROM_BASE 0x38
+#define PCI_CFG_BRG_INT_LINE 0x3c
+#define PCI_CFG_BRG_INT_PIN 0x3d
+#define PCI_CFG_BRIDGE_CONTROL 0x3e
+
+/* PCI Class definitions for find by class function */
+
+#define PCI_CLASS_PRE_PCI20 0x00
+#define PCI_CLASS_MASS_STORAGE 0x01
+#define PCI_CLASS_NETWORK_CTLR 0x02
+#define PCI_CLASS_DISPLAY_CTLR 0x03
+#define PCI_CLASS_MMEDIA_DEVICE 0x04
+#define PCI_CLASS_MEM_CTLR 0x05
+#define PCI_CLASS_BRIDGE_CTLR 0x06
+#define PCI_CLASS_COMM_CTLR 0x07
+#define PCI_CLASS_BASE_PERIPH 0x08
+#define PCI_CLASS_INPUT_DEVICE 0x09
+#define PCI_CLASS_DOCK_DEVICE 0x0A
+#define PCI_CLASS_PROCESSOR 0x0B
+#define PCI_CLASS_SERIAL_BUS 0x0C
+#define PCI_CLASS_UNDEFINED 0xFF
+
+/* PCI Subclass definitions */
+
+#define PCI_SUBCLASS_00 0x00
+#define PCI_SUBCLASS_01 0x01
+#define PCI_SUBCLASS_02 0x02
+#define PCI_SUBCLASS_03 0x03
+#define PCI_SUBCLASS_04 0x04
+#define PCI_SUBCLASS_05 0x05
+#define PCI_SUBCLASS_06 0x06
+#define PCI_SUBCLASS_07 0x07
+#define PCI_SUBCLASS_10 0x10
+#define PCI_SUBCLASS_20 0x20
+#define PCI_SUBCLASS_80 0x80
+
+/* Bridge Device subclasses */
+
+#define PCI_SUBCLASS_HOST_PCI_BRIDGE (PCI_SUBCLASS_00)
+#define PCI_SUBCLASS_ISA_BRIDGE (PCI_SUBCLASS_01)
+#define PCI_SUBCLASS_P2P_BRIDGE (PCI_SUBCLASS_04)
+#define PCI_SUBCLASS_PCMCIA_BRIDGE (PCI_SUBCLASS_05)
+#define PCI_SUBCLASS_CARDBUS_BRIDGE (PCI_SUBCLASS_07)
+
+/* Processor subclasses */
+
+#define PCI_SUBCLASS_PROCESSOR_386 (PCI_SUBCLASS_00)
+#define PCI_SUBCLASS_PROCESSOR_486 (PCI_SUBCLASS_01)
+#define PCI_SUBCLASS_PROCESSOR_PENTIUM (PCI_SUBCLASS_02)
+#define PCI_SUBCLASS_PROCESSOR_ALPHA (PCI_SUBCLASS_10)
+#define PCI_SUBCLASS_PROCESSOR_POWERPC (PCI_SUBCLASS_20)
+
+/* Serial bus subclasses */
+
+#define PCI_SUBCLASS_SERBUS_FIREWIRE (PCI_SUBCLASS_00)
+#define PCI_SUBCLASS_SERBUS_USB (PCI_SUBCLASS_03)
+
+/* Network subclasses */
+
+#define PCI_SUBCLASS_NET_ETHERNET (PCI_SUBCLASS_00)
+#define PCI_SUBCLASS_NET_TOKEN_RING (PCI_SUBCLASS_01)
+#define PCI_SUBCLASS_NET_FDDI (PCI_SUBCLASS_02)
+#define PCI_SUBCLASS_NET_ATM (PCI_SUBCLASS_03)
+
+/* Conditional defines for new configuration definitions */
+
+#define PCI_CMD_MASK 0xffff0000
+#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
+#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
+
+/* Vendor and Device ID's */
+
+/* Promise ATA */
+#define PCI_VENDOR_ID_PROMISE 0x105a
+#define PCI_DEVICE_ID_PROMISE_20265 0x0d30
+#define PCI_DEVICE_ID_PROMISE_20267 0x4d30
+#define PCI_DEVICE_ID_PROMISE_20246 0x4d33
+#define PCI_DEVICE_ID_PROMISE_20262 0x4d38
+#define PCI_DEVICE_ID_PROMISE_5300 0x5300
+
+/* Intel Ethernet */
+#define PCI_VENDOR_ID_INTEL 0x8086
+#define PCI_DEVICE_ID_INTEL_82559ER 0x1209
+#define PCI_DEVICE_ID_INTEL_82557 0x1229
+
+/* Cache Line Size - 32 32-bit value = 128 bytes */
+#ifndef PCI_CACHE_LINE_SIZE
+#define PCI_CACHE_LINE_SIZE 0x08
+#endif /* PCI_CACHE_LINE_SIZE */
+
+/* Latency Timer value - 255 PCI clocks */
+#ifndef PCI_LATENCY_TIMER
+#define PCI_LATENCY_TIMER 0x20
+#endif /* PCI_LATENCY_TIMER */
+
+#ifndef _ASMLANGUAGE
+int pci_dev_init(int b);
+int pci_dev_find(int vid, int devId, int idx,int *bus, int* dev, int* func);
+int pci_class_find(int class, int idx, int* bus, int* dev, int *func);
+int pci_config_inb(int b, int d, int f, int address, uint8 * pData);
+int pci_config_inw(int b, int d, int f, int address, uint16 * pData);
+int pci_config_inl(int b, int d, int f, int address, uint32 * pData);
+int pci_config_outb(int b, int d, int f, int address, uint8 data);
+int pci_config_outw(int b, int d, int f, int address, uint16 data);
+int pci_config_outl(int b, int d, int f, int address, uint32 data);
+int pci_special_cycle(int b, uint32 message);
+int pci_config_bdf_pack(int b, int d, int f);
+int pci_dev_config(int b, int d, int f, uint32 iobar, uint32 mbar, uint32 cm );
+int pci_config_modl(int b, int d, int f, int offset,
+ uint32 bitMask, uint32 data );
+int pci_config_modw(int b, int d, int f, int off,
+ uint16 bitMask, uint16 data );
+int pci_config_modb(int b, int d, int f, int offset,
+ uint8 bitMask, uint8 data );
+unsigned int pci_size_bar(unsigned int, unsigned long mask);
+#endif /* _ASMLANGUAGE */
+
+#endif /* __MPC824X_PCI */
cpu/mpc824x/start.o (.text)
common/board.o (.text)
ppc/ppcstring.o (.text)
- ppc/vsprintf.o (.text)
ppc/crc32.o (.text)
- ppc/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
return dram_size();
}
-
-
-/* temporarily here: to be removed: */
-
-
-int eth_init(bd_t *bis)
-{
- /* Initialize the device */
- return 0;
-}
-
-int eth_send(volatile void *packet, int length)
-{
- /* Send a packet */
- return 0;
-}
-
-int eth_rx(void)
-{
- /* Check for received packets */
- return 0;
-}
-
-void eth_halt(void)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+void pci_init (bd_t *dummy)
{
- /* stop ethernet */
+ pci_dev_init(0);
}
{
init_data_t * const idata = IDATA;
const int clock_divisor = 115200/baudrate;
- /* initialize_ns87308(); */
+ initialise_ns87308();
idata->console_addr = (void *)NS16550_init(0, clock_divisor);
}
void
cpu_init_f (void)
{
-/* MOUSSE, MUSENKI and SANDPOINT boards initialized in asm */
+/* MOUSSE and MUSENKI and boards initialized in asm */
#if (!defined(CONFIG_MOUSSE) && \
- !defined(CONFIG_MUSENKI) && \
- !defined(CONFIG_SANDPOINT) )
+ !defined(CONFIG_MUSENKI))
register unsigned long val;
CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
/* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
/*
* Calculate absolute address in FLASH and jump there
*----------------------------------------------------------------------*/
+#ifndef CONFIG_SANDPOINT
#ifndef CONFIG_CU824
#ifndef DEBUG
lis r3, CFG_MONITOR_BASE@h
blr
#endif
#endif
+#endif
in_flash:
-#if defined(CONFIG_SANDPOINT) || defined(CONFIG_MUSENKI)
+#if defined(CONFIG_MUSENKI)
bl early_init_f /* must be ASM: no stack yet! */
#endif
/*
uint immr, rev, m, k;
char buf[32];
- if ((pvr >> 16) != 0x0081)
+ if (((pvr >> 16) & 0xff) != 0x81)
return -1; /* whoops! not an MPC8260 */
rev = pvr & 0xff;
--- /dev/null
+The port was tested on a Sandpoint 8240 X3 board, with PPCBoot
+installed in the flash memory of the CPU card. Please use the
+following DIP switch settings:
+
+Motherboard:
+
+SW1.1: on SW1.2: on SW1.3: on SW1.4: on
+SW1.5: on SW1.6: on SW1.7: on SW1.8: on
+
+SW2.1: on SW2.2: on SW2.3: on SW2.4: on
+SW2.5: on SW2.6: on SW2.7: on SW2.8: on
+
+
+CPU Card:
+
+SW2.1: OFF SW2.2: OFF SW2.3: on SW2.4: on
+SW2.5: OFF SW2.6: OFF SW2.7: OFF SW2.8: OFF
+
+SW3.1: OFF SW3.2: on SW3.3: OFF SW3.4: OFF
+SW3.5: on SW3.6: OFF SW3.7: OFF SW3.8: on
+
#define CONFIG_MPC824X 1
#define CONFIG_MPC8240 1
#define CONFIG_SANDPOINT 1
+
+#if 0
#define USE_DINK32 1
+#else
+#undef USE_DINK32
+#endif
-#define CONFIG_BAUDRATE 115200
+#define CONFIG_BAUDRATE 9600
#define CONFIG_DRAM_SPEED 100 /* MHz */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET)
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 8 /* max number of command args */
+#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x00100000 /* default load address */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI /* include pci support */
+
+#define PCI_ENET_IOADDR 0x80000000
+#define PCI_ENET_MEMADDR 0x80000000
+
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
#define CFG_SDRAM_BASE 0x00000000
#if defined (USE_DINK32)
-#define CFG_MONITOR_LEN 0x00020000
+#define CFG_MONITOR_LEN 0x00030000
#define CFG_MONITOR_BASE 0x00090000
#define CFG_RAMBOOT 1
#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_INIT_RAM_END (CFG_INIT_RAM_ADDR + 0x10000)
+#define CFG_INIT_RAM_END 0x10000
#define CFG_INIT_DATA_SIZE 256 /* size in bytes reserved for initial data */
#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
#else
#undef CFG_RAMBOOT
+#define CFG_MONITOR_LEN 0x00030000
+#define CFG_MONITOR_BASE TEXT_BASE
+
+/*#define CFG_INIT_DATA_SIZE 256*/
+#define CFG_INIT_DATA_SIZE 128
+
+#define CFG_INIT_RAM_ADDR 0x40000000
+#define CFG_INIT_RAM_END 0x1000
+#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+
#endif
#define CFG_FLASH_BASE 0xFFF00000
+#if 0
#define CFG_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */
+#else
+#define CFG_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */
+#endif
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_OFFSET 0x00008000 /* Offset of Environment Sector */
-#define CFG_ENV_SIZE 0x00004000 /* Total Size of Environment Sector */
+#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
#define CFG_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
#define CFG_FLASH_RANGE_SIZE 0x01000000
-#define FLASH_BASE0_PRELIM 0xFFF80000 /* sandpoint flash */
+#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM }
+#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
#define CFG_ROMNAL 7 /*rom/flash next access time */
#define CFG_ROMFAL 11 /*rom/flash access time */
-#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */
+#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */
+
/* the following are for SDRAM only*/
-#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
+#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
#define CFG_REFREC 8 /* Refresh to activate interval */
-#define CFG_RDLAT 3 /* data latency from read command */
+#define CFG_RDLAT 4 /* data latency from read command */
#define CFG_PRETOACT 3 /* Precharge to activate interval */
#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
#define CFG_ACTTORW 3 /* Activate to R/W */
-#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */
+#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
0x00000 for a start address, or 0xfffff for an end address*/
#define CFG_BANK0_START 0x00000000
-#define CFG_BANK0_END 0x03ffffff
+#define CFG_BANK0_END 0x01ffffff
+#define CFG_BANK0_ENABLE 1
#define CFG_BANK1_START 0x04000000
#define CFG_BANK1_END 0x07ffffff
+#define CFG_BANK1_ENABLE 0
#define CFG_BANK2_START 0x08000000
#define CFG_BANK2_END 0x0bffffff
+#define CFG_BANK2_ENABLE 0
#define CFG_BANK3_START 0x0c000000
#define CFG_BANK3_END 0x0fffffff
+#define CFG_BANK3_ENABLE 0
#define CFG_BANK4_START 0x00000000
#define CFG_BANK4_END 0x00000000
+#define CFG_BANK4_ENABLE 0
#define CFG_BANK5_START 0x00000000
#define CFG_BANK5_END 0x00000000
+#define CFG_BANK5_ENABLE 0
#define CFG_BANK6_START 0x00000000
#define CFG_BANK6_END 0x00000000
+#define CFG_BANK6_ENABLE 0
#define CFG_BANK7_START 0x00000000
#define CFG_BANK7_END 0x00000000
-
+#define CFG_BANK7_ENABLE 0
/*
* Memory bank enable bitmask, specifying which of the banks defined above
are actually present. MSB is for bank #7, LSB is for bank #0.
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
/* stack in DCACHE @ 1GB (no backing mem) */
+#if defined(USE_DINK32)
#define CFG_IBAT1L (0x40000000 | BATL_PP_00 )
#define CFG_IBAT1U (0x40000000 | BATU_BL_128K )
+#else
+#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#endif
/* PCI memory */
#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define BATL_BRPN_MSK 0xfffe0000
#define BATL_WIMG_MSK 0x00000078
-#ifdef CONFIG_SANDPOINT
-/* The below defines are not correct, but are in use
- * for Sandpoint.
- */
-#define BATL_WRITETHROUGH 0x00000008
-#define BATL_CACHEINHIBIT 0x00000010
-#define BATL_MEMCOHERENCE 0x00000020
-#define BATL_GUARDEDSTORAGE 0x00000040
-#else
+
#define BATL_WRITETHROUGH 0x00000040
#define BATL_CACHEINHIBIT 0x00000020
#define BATL_MEMCOHERENCE 0x00000010
#define BATL_GUARDEDSTORAGE 0x00000008
-#endif /* CONFIG_SANDPOINT */
+
#define BATL_PP_MSK 0x00000003
#define BATL_PP_00 0x00000000 /* No access */
#define BATL_PP_01 0x00000001 /* Read-only */
projects / users / rw / ppcboot.git / commitdiff