gt->awake = intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ);
        GEM_BUG_ON(!gt->awake);
 
-       if (NEEDS_RC6_CTX_CORRUPTION_WA(i915))
-               intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
-
        intel_rc6_unpark(>->rc6);
        intel_rps_unpark(>->rps);
        i915_pmu_gt_unparked(i915);
        /* Everything switched off, flush any residual interrupt just in case */
        intel_synchronize_irq(i915);
 
-       if (NEEDS_RC6_CTX_CORRUPTION_WA(i915)) {
-               intel_rc6_ctx_wa_check(>->rc6);
-               intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
-       }
-
        GEM_BUG_ON(!wakeref);
        intel_display_power_put(i915, POWER_DOMAIN_GT_IRQ, wakeref);
 
 
  * Check if an RC6 CTX corruption has happened since the last check and if so
  * disable RC6 and runtime power management.
 */
-void intel_rc6_ctx_wa_check(struct intel_rc6 *rc6)
+static bool intel_rc6_ctx_wa_check(struct intel_rc6 *rc6)
 {
        struct drm_i915_private *i915 = rc6_to_i915(rc6);
 
        if (!NEEDS_RC6_CTX_CORRUPTION_WA(i915))
-               return;
+               return false;
 
        if (rc6->ctx_corrupted)
-               return;
+               return false;
 
        if (!intel_rc6_ctx_corrupted(rc6))
-               return;
+               return false;
 
        dev_notice(i915->drm.dev,
                   "RC6 context corruption, disabling runtime power management\n");
 
-       intel_rc6_disable(rc6);
        rc6->ctx_corrupted = true;
 
-       return;
+       return true;
 }
 
 static void __intel_rc6_disable(struct intel_rc6 *rc6)
        else if (INTEL_GEN(i915) >= 6)
                gen6_rc6_enable(rc6);
 
+       if (NEEDS_RC6_CTX_CORRUPTION_WA(i915))
+               rc6->ctl_enable = 0;
+
        intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 
        /* rc6 is ready, runtime-pm is go! */
        if (!rc6->enabled)
                return;
 
+       if (unlikely(intel_rc6_ctx_wa_check(rc6))) {
+               intel_rc6_disable(rc6);
+               return;
+       }
+
        /* Turn off the HW timers and go directly to rc6 */
        set(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE);
        set(uncore, GEN6_RC_STATE, 0x4 << RC_SW_TARGET_STATE_SHIFT);
 
 u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, i915_reg_t reg);
 u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg);
 
-void intel_rc6_ctx_wa_check(struct intel_rc6 *rc6);
 void intel_rc6_ctx_wa_resume(struct intel_rc6 *rc6);
 
 #endif /* INTEL_RC6_H */