drm/i915/snps: use div32 version of MPLLB word clock for UHBR

The mode set sequence for 128b/132b requires setting the div32 version
of MPLLB clock.

Bspec: 53880, 54128
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211202144456.2541305-1-jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index c2251218a39e0545bc6d608459af4467b2e7c4f2..09f405e4d363f6e40ffdee900677436675ffd49a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -186,6 +186,7 @@ static const struct intel_mpllb_state dg2_dp_uhbr10_100 = {
                REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
                REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
                REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
+               REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) |
                REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
        .mpllb_div2 =
                REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
@@ -369,6 +370,7 @@ static const struct intel_mpllb_state dg2_dp_uhbr10_38_4 = {
                REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
                REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
                REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
+               REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) |
                REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
        .mpllb_div2 =
                REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b0f5865482a0535bf90a605145c7b2b5b9be4e45..1a135a73dcd94955d15b8243643485ad4d2d0a6a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2247,6 +2247,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   SNPS_PHY_MPLLB_DP2_MODE              REG_BIT(9)
 #define   SNPS_PHY_MPLLB_WORD_DIV2_EN          REG_BIT(8)
 #define   SNPS_PHY_MPLLB_TX_CLK_DIV            REG_GENMASK(7, 5)
+#define   SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL    REG_BIT(0)
 
 #define SNPS_PHY_MPLLB_FRACN1(phy)             _MMIO_SNPS(phy, 0x168008)
 #define   SNPS_PHY_MPLLB_FRACN_EN              REG_BIT(31)