drm/i915: Do not set any power wells when there is no display

Power wells are only part of display block and not necessary when
running a headless driver.

Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210408203150.237947-2-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 9419ae8c6111b6c9d452365977915392d932f810..53311b9764dc52f17386787795fd351264872828 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4674,7 +4674,10 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
         * The enabling order will be from lower to higher indexed wells,
         * the disabling order is reversed.
         */
-       if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
+       if (!HAS_DISPLAY(dev_priv)) {
+               power_domains->power_well_count = 0;
+               err = 0;
+       } else if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
                err = set_power_wells_mask(power_domains, tgl_power_wells,
                                           BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
        } else if (IS_ROCKETLAKE(dev_priv)) {