.send_immediate_char =          neo_send_immediate_char
 };
 
-static uint dgnc_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
+static uint dgnc_offset_table[8] = { 0x01, 0x02, 0x04, 0x08,
+                                    0x10, 0x20, 0x40, 0x80 };
 
 /*
  * This function allows calls to ensure that all outstanding
        writeb(efr, &ch->ch_neo_uart->efr);
 
        /* Turn on table D, with 8 char hi/low watermarks */
-       writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
+       writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY),
+               &ch->ch_neo_uart->fctr);
 
        /* Feed the UART our trigger levels */
        writeb(8, &ch->ch_neo_uart->tfifo);
        /* Turn on UART enhanced bits */
        writeb(efr, &ch->ch_neo_uart->efr);
 
-       writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
+       writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY),
+               &ch->ch_neo_uart->fctr);
        ch->ch_r_watermark = 4;
 
        writeb(32, &ch->ch_neo_uart->rfifo);
        /* Turn on UART enhanced bits */
        writeb(efr, &ch->ch_neo_uart->efr);
 
-       writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
+       writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY),
+              &ch->ch_neo_uart->fctr);
        ch->ch_r_watermark = 4;
 
        writeb(32, &ch->ch_neo_uart->rfifo);
        writeb(efr, &ch->ch_neo_uart->efr);
 
        /* Turn on table D, with 8 char hi/low watermarks */
-       writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
+       writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY),
+               &ch->ch_neo_uart->fctr);
 
        writeb(8, &ch->ch_neo_uart->tfifo);
        ch->ch_t_tlevel = 8;
        writeb(efr, &ch->ch_neo_uart->efr);
 
        /* Turn on table D, with 8 char hi/low watermarks */
-       writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
+       writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY),
+               &ch->ch_neo_uart->fctr);
 
        ch->ch_r_watermark = 0;
 
        writeb(efr, &ch->ch_neo_uart->efr);
 
        /* Turn on table D, with 8 char hi/low watermarks */
-       writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
+       writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY),
+               &ch->ch_neo_uart->fctr);
 
        ch->ch_r_watermark = 0;
 
 static inline void neo_set_new_start_stop_chars(struct channel_t *ch)
 {
        /* if hardware flow control is set, then skip this whole thing */
-       if (ch->ch_digi.digi_flags & (CTSPACE | RTSPACE) || ch->ch_c_cflag & CRTSCTS)
+       if (ch->ch_digi.digi_flags & (CTSPACE | RTSPACE) ||
+           ch->ch_c_cflag & CRTSCTS)
                return;
 
        /* Tell UART what start/stop chars it should be looking for */
                        break;
 
                /*
-                * Yank off the upper 2 bits, which just show that the FIFO's are enabled.
+                * Yank off the upper 2 bits,
+                * which just show that the FIFO's are enabled.
                 */
                isr &= ~(UART_17158_IIR_FIFO_ENABLED);
 
                };
 
                /* Only use the TXPrint baud rate if the terminal unit is NOT open */
-               if (!(ch->ch_tun.un_flags & UN_ISOPEN) && (un->un_type == DGNC_PRINT))
+               if (!(ch->ch_tun.un_flags & UN_ISOPEN) &&
+                   (un->un_type == DGNC_PRINT))
                        baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
                else
                        baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
 
                jindex = baud;
 
-               if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) && (jindex < 16))
+               if ((iindex >= 0) && (iindex < 4) &&
+                   (jindex >= 0) && (jindex < 16))
                        baud = bauds[iindex][jindex];
                else
                        baud = 0;
                neo_set_cts_flow_control(ch);
        } else if (ch->ch_c_iflag & IXON) {
                /* If start/stop is set to disable, then we should disable flow control */
-               if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE))
+               if ((ch->ch_startc == _POSIX_VDISABLE) ||
+                   (ch->ch_stopc == _POSIX_VDISABLE))
                        neo_set_no_output_flow_control(ch);
                else
                        neo_set_ixon_flow_control(ch);
                neo_set_rts_flow_control(ch);
        } else if (ch->ch_c_iflag & IXOFF) {
                /* If start/stop is set to disable, then we should disable flow control */
-               if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE))
+               if ((ch->ch_startc == _POSIX_VDISABLE) ||
+                   (ch->ch_stopc == _POSIX_VDISABLE))
                        neo_set_no_input_flow_control(ch);
                else
                        neo_set_ixoff_flow_control(ch);
                linestatus = 0;
 
                /* Copy data from uart to the queue */
-               memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
+               memcpy_fromio(ch->ch_rqueue + head,
+                             &ch->ch_neo_uart->txrxburst, n);
 
                /*
                 * Since RX_FIFO_DATA_ERROR was 0, we are guaranteed
                 * we don't miss our TX FIFO emptys.
                 */
                if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
-                       linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
+                       linestatus &= ~(UART_LSR_THRE |
+                                       UART_17158_TX_AND_FIFO_CLR);
                        ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
                }
 
                        qleft++;
                }
 
-               memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
+               memcpy_fromio(ch->ch_rqueue + head,
+                             &ch->ch_neo_uart->txrxburst, 1);
                ch->ch_equeue[head] = (unsigned char)linestatus;
 
                /* Ditch any remaining linestatus value. */
        if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
                return;
 
-       writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
+       writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
+              &ch->ch_neo_uart->isr_fcr);
        neo_pci_posting_flush(ch->ch_bd);
 
        for (i = 0; i < 10; i++) {
        if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
                return;
 
-       writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
+       writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR),
+              &ch->ch_neo_uart->isr_fcr);
        neo_pci_posting_flush(ch->ch_bd);
 
        for (i = 0; i < 10; i++) {
                                ch->ch_tun.un_flags |= (UN_EMPTY);
                        }
 
-                       writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_neo_uart->txrx);
+                       writeb(ch->ch_wqueue[ch->ch_w_tail],
+                              &ch->ch_neo_uart->txrx);
                        ch->ch_w_tail++;
                        ch->ch_w_tail &= WQUEUEMASK;
                        ch->ch_txcount++;
                        ch->ch_tun.un_flags |= (UN_EMPTY);
                }
 
-               memcpy_toio(&ch->ch_neo_uart->txrxburst, ch->ch_wqueue + tail, s);
+               memcpy_toio(&ch->ch_neo_uart->txrxburst,
+                           ch->ch_wqueue + tail, s);
 
                /* Add and flip queue if needed */
                tail = (tail + s) & WQUEUEMASK;
 
        /* Clear out UART and FIFO */
        readb(&ch->ch_neo_uart->txrx);
-       writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
+       writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
+              &ch->ch_neo_uart->isr_fcr);
        readb(&ch->ch_neo_uart->lsr);
        readb(&ch->ch_neo_uart->msr);
 
        neo_pci_posting_flush(ch->ch_bd);
 }
 
-static unsigned int neo_read_eeprom(unsigned char __iomem *base, unsigned int address)
+static unsigned int neo_read_eeprom(unsigned char __iomem *base,
+                                   unsigned int address)
 {
        unsigned int enable;
        unsigned int bits;